[llvm] Don't use Optional::hasValue (NFC)

This patch replaces Optional::hasValue with the implicit cast to bool
in conditionals only.

Revert "Don't use Optional::hasValue (NFC)"

This reverts commit aa8feeefd3ac6c78ee8f67bf033976fc7d68bc6d.

Don't use Optional::hasValue (NFC)

[PowerPC] add a new pass to expand ctr loop pseudos

This patch implements a new way to generate the CTR loops. Now the
intrinsics inserted in hardware loop pass will be mapped to pseudo
instructions

[PowerPC] add a new pass to expand ctr loop pseudos

This patch implements a new way to generate the CTR loops. Now the
intrinsics inserted in hardware loop pass will be mapped to pseudo
instructions and these pseudo instructions will be expanded to CTR
loop or normal compare+branch loop in this post ISEL pass.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D122125

show more ...

Cleanup includes: DebugInfo & CodeGen

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121332

mark getTargetTransformInfo and getTargetIRAnalysis as const

Seems like this can be const, since Passes shouldn't modify it.

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D1

mark getTargetTransformInfo and getTargetIRAnalysis as const

Seems like this can be const, since Passes shouldn't modify it.

Reviewed By: wsmoses

Differential Revision: https://reviews.llvm.org/D120518

show more ...

[PowerPC] Option controling scalar MASS convertion

differential: https://reviews.llvm.org/D119035

reviewer: bmahjour

[PowerPC] Scalar IBM MASS library conversion pass

This patch introduces the conversions from math function calls
to MASS library calls. To resolves calls generated with these conversions, one
need t

[PowerPC] Scalar IBM MASS library conversion pass

This patch introduces the conversions from math function calls
to MASS library calls. To resolves calls generated with these conversions, one
need to link libxlopt.a library. This patch is tested on PowerPC Linux and AIX.

Differential: https://reviews.llvm.org/D101759

Reviewer: bmahjour

show more ...

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

show more ...

[PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand

This patch uses AtomicExpandPass to implement quadword lock free atomic operations. It adopts the method introduced i

[PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand

This patch uses AtomicExpandPass to implement quadword lock free atomic operations. It adopts the method introduced in https://reviews.llvm.org/D47882, which expand atomic operations post RA to avoid spilling that might prevent LL/SC progress.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D103614

show more ...

[PowerPC] Move PPCBranchSelector as close to asm printer as possible

Currently, PPCBranchSelector is not immediately preceding asm printer pass. `-debug-pass=Structure` gives
```
PowerPC Branc

[PowerPC] Move PPCBranchSelector as close to asm printer as possible

Currently, PPCBranchSelector is not immediately preceding asm printer pass. `-debug-pass=Structure` gives
```
PowerPC Branch Selector
Contiguously Lay Out Funclets
StackMap Liveness Analysis
Live DEBUG_VALUE analysis
Lazy Machine Block Frequency Analysis
Machine Optimization Remark Emitter
Linux PPC Assembly Printer
```
After the patch
```
Contiguously Lay Out Funclets
StackMap Liveness Analysis
Live DEBUG_VALUE analysis
PowerPC Branch Selector
Lazy Machine Block Frequency Analysis
Machine Optimization Remark Emitter
Linux PPC Assembly Printer
```

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D104762

show more ...

Normalize interaction with boolean attributes

Such attributes can either be unset, or set to "true" or "false" (as string).
throughout the codebase, this led to inelegant checks ranging from

Normalize interaction with boolean attributes

Such attributes can either be unset, or set to "true" or "false" (as string).
throughout the codebase, this led to inelegant checks ranging from

if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")

to

if (Fn->hasAttribute("no-jump-tables") && Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")

Introduce a getValueAsBool that normalize the check, with the following
behavior:

no attributes or attribute set to "false" => return false
attribute set to "true" => return true

Differential Revision: https://reviews.llvm.org/D99299

show more ...

[NFC] [PowerPC] Determine Endianness in PPCTargetMachine

The TargetMachine uses the triple to determine endianness. Just
use that logic rather than replicating it in PPCSubtarget.

Differential revi

[NFC] [PowerPC] Determine Endianness in PPCTargetMachine

The TargetMachine uses the triple to determine endianness. Just
use that logic rather than replicating it in PPCSubtarget.

Differential revision: https://reviews.llvm.org/D98674

show more ...

[PowerPC] Change target data layout for 16-byte stack alignment

This changes the target data layout to make stack align to 16 bytes
on Power10. Before this change, stack was being aligned to 32 byte

[PowerPC] Change target data layout for 16-byte stack alignment

This changes the target data layout to make stack align to 16 bytes
on Power10. Before this change, stack was being aligned to 32 bytes.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D96265

show more ...

[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.

To do this while supporting the existing functionality in SelectionDAG of using
PGO info, we add the ProfileSummaryInfo and

[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.

To do this while supporting the existing functionality in SelectionDAG of using
PGO info, we add the ProfileSummaryInfo and LazyBlockFrequencyInfo analysis
dependencies to the instruction selector pass.

Then, use the predicate to generate constant pool loads for f32 materialization,
if we're targeting optsize/minsize.

Differential Revision: https://reviews.llvm.org/D97732

show more ...

[PowerPC] Only use some extend mne if assembler is modern enough

Legacy AIX assembly might not support all extended mnes,
add one feature bit to control the generation in MC,
and avoid generating th

[PowerPC] Only use some extend mne if assembler is modern enough

Legacy AIX assembly might not support all extended mnes,
add one feature bit to control the generation in MC,
and avoid generating them by default on AIX.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94458

show more ...

[PowerPC] Delete remnant isOSDarwin references

[PowerPC] Add the LLVM triple for powerpcle [1/5]

Add a triple for powerpcle-*-*.

This is a little-endian encoding of the 32-bit PowerPC ABI, useful in certain niche situations:

1) A loader such a

[PowerPC] Add the LLVM triple for powerpcle [1/5]

Add a triple for powerpcle-*-*.

This is a little-endian encoding of the 32-bit PowerPC ABI, useful in certain niche situations:

1) A loader such as the FreeBSD loader which will be loading a little endian kernel. This is required for PowerPC64LE to load properly in pseries VMs.
Such a loader is implemented as a freestanding ELF32 LSB binary.

2) Userspace emulation of a 32-bit LE architecture such as x86 on 64-bit hosts such as PowerPC64LE with tools like box86 requires having a 32-bit LE toolchain and library set, as they operate by translating only the main binary and switching to native code when making library calls.

3) The Void Linux for PowerPC project is experimenting with running an entire powerpcle userland.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D93918

show more ...

[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

This patch legalizes the v256i1 and v512i1 types that will be used for MMA.

It implements loads and stores of these

[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types

This patch legalizes the v256i1 and v512i1 types that will be used for MMA.

It implements loads and stores of these types.
v256i1 is a pair of VSX registers, so for this type, we load/store the two
underlying registers. v512i1 is used for MMA accumulators. So in addition to
loading and storing the 4 associated VSX registers, we generate instructions to
prime (copy the VSX registers to the accumulator) after loading and unprime
(copy the accumulator back to the VSX registers) before storing.

This patch also adds the UACC register class that is necessary to implement the
loads and stores. This class represents accumulator in their unprimed form and
allow the distinction between primed and unprimed accumulators to avoid invalid
copies of the VSX registers associated with primed accumulators.

Differential Revision: https://reviews.llvm.org/D84968

show more ...

Reland "[PowerPC] Implement instruction clustering for stores"

Commit 3c0b3250 introduced store fusion for PowerPC target, but it
brought failure under UB sanitizer and was reverted. This patch fixe

Reland "[PowerPC] Implement instruction clustering for stores"

Commit 3c0b3250 introduced store fusion for PowerPC target, but it
brought failure under UB sanitizer and was reverted. This patch fixes
them.

show more ...

[PPC][GlobalISel] Add initial GlobalIsel infrastructure

This adds the initial GlobalISel skeleton for PowerPC. It can only run
ir-translator and legalizer for `ret void`.

This is largely based on t

[PPC][GlobalISel] Add initial GlobalIsel infrastructure

This adds the initial GlobalISel skeleton for PowerPC. It can only run
ir-translator and legalizer for `ret void`.

This is largely based on the initial GlobalISel patch for RISCV
(https://reviews.llvm.org/D65219).

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D83100

show more ...

Revert "[PowerPC] Implement instruction clustering for stores"

This reverts commit 3c0b3250230b3847a2a47dfeacfdb794c2285f02, (along
with ea795304 and bb39eb9e) since it breaks test with UB sanitizer.

[PowerPC] Implement instruction clustering for stores

On Power10, it's profitable to schedule some stores with adjacent target
address together. This patch implements this feature.

Reviewed By: ste

[PowerPC] Implement instruction clustering for stores

On Power10, it's profitable to schedule some stores with adjacent target
address together. This patch implements this feature.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D86754

show more ...

[Attributes] Add a method to check if an Attribute has AttrKind None. Use instead of hasAttribute(Attribute::None)

There's a special case in hasAttribute for None when pImpl is null. If pImpl is not

[Attributes] Add a method to check if an Attribute has AttrKind None. Use instead of hasAttribute(Attribute::None)

There's a special case in hasAttribute for None when pImpl is null. If pImpl is not null we dispatch to pImpl->hasAttribute which will always return false for Attribute::None.

So if we just want to check for None its sufficient to just check that pImpl is null. Which can even be done inline.

This patch adds a helper for that case which I hope will speed up our getSubtargetImpl implementations.

Differential Revision: https://reviews.llvm.org/D86744

show more ...

Re-land "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

This reverts commit bf544fa1c3cb80f24d85e84559fb11193846259f.

Fixed the typo in PPCInstrInfo.cpp.