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Searched refs:OpVT (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DRuntimeLibcalls.h47 Libcall getFPEXT(EVT OpVT, EVT RetVT);
51 Libcall getFPROUND(EVT OpVT, EVT RetVT);
55 Libcall getFPTOSINT(EVT OpVT, EVT RetVT);
59 Libcall getFPTOUINT(EVT OpVT, EVT RetVT);
63 Libcall getSINTTOFP(EVT OpVT, EVT RetVT);
67 Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
H A DSelectionDAG.h667 SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT);
903 SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp234 if (OpVT == MVT::f16) { in getFPEXT()
267 if (OpVT == MVT::f32) in getFPROUND()
269 if (OpVT == MVT::f64) in getFPROUND()
271 if (OpVT == MVT::f80) in getFPROUND()
278 if (OpVT == MVT::f32) in getFPROUND()
280 if (OpVT == MVT::f64) in getFPROUND()
283 if (OpVT == MVT::f64) in getFPROUND()
285 if (OpVT == MVT::f80) in getFPROUND()
292 if (OpVT == MVT::f80) in getFPROUND()
309 if (OpVT == MVT::f16) { in getFPTOSINT()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp169 EVT OpVT = N->getOperand(0 + Offset).getValueType(); in SoftenFloatRes_Unary() local
529 EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType(); in SoftenFloatRes_FP_EXTEND() local
1124 EVT OpVT = N->getOperand(0 + Offset).getValueType(); in SoftenFloatOp_Unary() local
1140 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT, in SoftenFloatOp_LROUND()
1150 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT, in SoftenFloatOp_LLROUND()
1160 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT, in SoftenFloatOp_LRINT()
1170 return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT, in SoftenFloatOp_LLRINT()
2074 if (OpVT == MVT::f16) { in GetPromotionOpcode()
2078 } else if (OpVT == MVT::bf16) { in GetPromotionOpcode()
2130 EVT OpVT = Op->getValueType(0); in PromoteFloatOp_BITCAST() local
[all …]
H A DTargetLowering.cpp3679 EVT OpVT = N0.getValueType(); in foldSetCCWithAnd() local
3715 assert(OpVT.isInteger()); in foldSetCCWithAnd()
3926 EVT OpVT = N0.getValueType(); in foldSetCCWithBinOp() local
4050 EVT OpVT = N0.getValueType(); in foldSetCCWithRotate() local
4109 EVT OpVT = N0.getValueType(); in foldSetCCWithFunnelShift() local
4139 EVT OpVT = N0.getValueType(); in SimplifySetCC() local
4995 N0 = DAG.getNOT(dl, Temp, OpVT); in SimplifySetCC()
5004 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5011 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5018 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
[all …]
H A DSelectionDAG.cpp1389 EVT OpVT = Op.getValueType(); in getZeroExtendInReg() local
1399 if (OpVT == VT) in getZeroExtendInReg()
1403 return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT)); in getZeroExtendInReg()
1439 switch (TLI->getBooleanContents(OpVT)) { in getBoolConstant()
2320 EVT OpVT = N1.getValueType(); in FoldSetCC() local
2344 if (OpVT.isInteger()) { in FoldSetCC()
3862 EVT OpVT = Val.getValueType(); in isKnownToBeAPowerOfTwo() local
4908 EVT OpVT = Op.getValueType(); in foldCONCAT_VECTORS() local
6120 Ops.push_back(getUNDEF(OpVT)); in getNode()
11012 EVT OpVT = Op.getValueType(); in matchBinOpReduction() local
[all …]
H A DLegalizeVectorTypes.cpp334 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_FP_ROUND() local
340 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_FP_ROUND()
386 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_UnaryOp() local
398 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_UnaryOp()
417 EVT OpVT = Op.getValueType(); in ScalarizeVecRes_VecInregOp() local
418 EVT OpEltVT = OpVT.getVectorElementType(); in ScalarizeVecRes_VecInregOp()
452 EVT OpVT = Cond.getValueType(); in ScalarizeVecRes_VSELECT() local
460 EVT VT = OpVT.getVectorElementType(); in ScalarizeVecRes_VSELECT()
481 VecBool = TLI.getBooleanContents(OpVT); in ScalarizeVecRes_VSELECT()
569 EVT OpVT = LHS.getValueType(); in ScalarizeVecRes_SETCC() local
[all …]
H A DScheduleDAGSDNodes.cpp481 EVT OpVT = N->getOperand(i).getValueType(); in AddSchedEdges() local
482 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!"); in AddSchedEdges()
483 bool isChain = OpVT == MVT::Other; in AddSchedEdges()
H A DLegalizeTypes.cpp314 EVT OpVT = Op.getValueType(); in run() local
315 switch (getTypeAction(OpVT)) { in run()
H A DLegalizeVectorOps.cpp452 MVT OpVT = Node->getOperand(0).getSimpleValueType(); in LegalizeOp() local
454 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
1453 MVT OpVT = Node->getOperand(0).getSimpleValueType(); in ExpandSETCC() local
1456 if (TLI.getCondCodeAction(CCCode, OpVT) != TargetLowering::Expand) { in ExpandSETCC()
H A DInstrEmitter.cpp387 MVT OpVT = Op.getSimpleValueType(); in AddOperand() local
392 TLI->isTypeLegal(OpVT) in AddOperand()
393 ? TLI->getRegClassFor(OpVT, in AddOperand()
H A DDAGCombiner.cpp5423 EVT OpVT = LL.getValueType(); in foldLogicOfSetCCs() local
5425 if (VT != getSetCCResultType(OpVT)) in foldLogicOfSetCCs()
5427 if (OpVT != RL.getValueType()) in foldLogicOfSetCCs()
5432 bool IsInteger = OpVT.isInteger(); in foldLogicOfSetCCs()
15588 EVT OpVT = N0.getValueType(); in visitSINT_TO_FP() local
15603 if (!hasOperation(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
15604 hasOperation(ISD::UINT_TO_FP, OpVT)) { in visitSINT_TO_FP()
15640 EVT OpVT = N0.getValueType(); in visitUINT_TO_FP() local
15656 hasOperation(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
20872 if (TLI.isTypeLegal(OpVT)) in combineConcatVectorOfScalars()
[all …]
H A DLegalizeIntegerTypes.cpp1945 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy; in PromoteIntOp_SELECT() local
1946 Cond = PromoteTargetBoolean(Cond, OpVT); in PromoteIntOp_SELECT()
5315 EVT OpVT = Op.getValueType(); in PromoteIntRes_BUILD_VECTOR() local
5320 if (OpVT.bitsLT(NOutVTElem)) { in PromoteIntRes_BUILD_VECTOR()
5325 if (OpVT == MVT::i1 && Op.getOpcode() == ISD::Constant) in PromoteIntRes_BUILD_VECTOR()
5387 EVT OpVT = Op.getValueType(); in PromoteIntRes_CONCAT_VECTORS() local
5388 if (getTypeAction(OpVT) == TargetLowering::TypePromoteInteger) in PromoteIntRes_CONCAT_VECTORS()
5391 assert(getTypeAction(OpVT) == TargetLowering::TypeLegal && in PromoteIntRes_CONCAT_VECTORS()
5394 if (OpVT.getVectorElementType().getScalarSizeInBits() < in PromoteIntRes_CONCAT_VECTORS()
5397 OpVT.changeVectorElementType(MaxElementVT)); in PromoteIntRes_CONCAT_VECTORS()
H A DLegalizeDAG.cpp1050 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType(); in LegalizeOp() local
1053 Action = TLI.getCondCodeAction(CCCode, OpVT); in LegalizeOp()
1059 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); in LegalizeOp()
1900 EVT OpVT = Node->getOperand(0).getValueType(); in ExpandBUILD_VECTOR() local
1942 if (OpVT==EltVT) in ExpandBUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2474 EVT OpVT = Op.getOperand(0).getValueType(); in LowerSINT_TO_FP() local
2475 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); in LowerSINT_TO_FP()
2477 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; in LowerSINT_TO_FP()
2481 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { in LowerSINT_TO_FP()
2482 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 in LowerSINT_TO_FP()
2489 if (!TLI.isTypeLegal(OpVT)) in LowerSINT_TO_FP()
2494 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; in LowerSINT_TO_FP()
2523 EVT OpVT = Op.getOperand(0).getValueType(); in LowerUINT_TO_FP() local
2524 assert(OpVT == MVT::i32 || OpVT == MVT::i64); in LowerUINT_TO_FP()
2528 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) in LowerUINT_TO_FP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6747 MVT WideOpVT = OpVT; in insert1BitVector()
19237 DAG.getVectorShuffle(OpVT, DL, Op1, DAG.getUNDEF(OpVT), Mask), CC); in lower1BitShuffle()
20123 assert(OpVT.is128BitVector() && OpVT.isInteger() && OpVT != MVT::v2i64 && in LowerSCALAR_TO_VECTOR()
20128 if (OpVT == MVT::v4i32 || (OpVT == MVT::v8i16 && Subtarget.hasFP16())) in LowerSCALAR_TO_VECTOR()
23322 assert((OpVT == MVT::f32 || OpVT == MVT::f64) && in LowerFGETSIGN()
28801 MVT OpVT = VT; in LowerCTLZ() local
28812 OpVT = MVT::i32; in LowerCTLZ()
43611 if (OpVT != MVT::f32 && OpVT != MVT::f64) in scalarizeExtEltFP()
48126 MVT OpVT = in canonicalizeBitSelect() local
52102 return DAG.getNode(ISD::AND, DL, OpVT, DAG.getNOT(DL, N1, OpVT), in combineSetCC()
[all …]
H A DX86InstrSSE.td2249 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
5812 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
5820 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>,
6534 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6542 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>,
7756 ValueType OpVT, X86FoldableSchedWrite Sched,
7771 (OpVT (X86VPermv VR256:$src1,
7797 (OpVT (X86VPermi (mem_frag addr:$src1),
8048 multiclass GF2P8MULB_rm<string OpcodeStr, ValueType OpVT,
8061 [(set RC:$dst, (OpVT (X86GF2P8mulb RC:$src1,
[all …]
H A DX86InstrFMA.td391 X86MemOperand x86memop, ValueType OpVT, SDPatternOperator OpNode,
399 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG,
H A DX86ISelDAGToDAG.cpp588 EVT OpVT = N->getOperand(0).getValueType(); in isLegalMaskCompare() local
592 OpVT = N->getOperand(1).getValueType(); in isLegalMaskCompare()
593 if (OpVT.is256BitVector() || OpVT.is128BitVector()) in isLegalMaskCompare()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1783 EVT OpVT = Ops[0].getValueType(); in PerformDAGCombine() local
1784 if (InVal.getValueType() != OpVT) in PerformDAGCombine()
1785 InVal = OpVT.bitsGT(InVal.getValueType()) ? in PerformDAGCombine()
1786 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1787 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1576 if (OpVT != MVT::i32 && OpVT != MVT::i64) in shouldExpandGetActiveLaneMask()
4109 EVT OpVT = Op.getValueType(); in LowerBITCAST() local
4112 if (useSVEForFixedLengthVectorVT(OpVT)) in LowerBITCAST()
4115 if (OpVT.isScalableVector()) { in LowerBITCAST()
4135 if (OpVT != MVT::f16 && OpVT != MVT::bf16) in LowerBITCAST()
11915 EVT OpVT = Op.getOperand(0).getValueType(); in LowerTRUNCATE() local
15081 EVT OpVT = N0.getValueType(); in performLastTrueTestVectorCombine() local
15083 if (!OpVT.isScalableVector() || OpVT.getVectorElementType() != MVT::i1) in performLastTrueTestVectorCombine()
21422 EVT OpVT = Op.getValueType(); in LowerPredReductionToSVE() local
21425 if (!OpVT.isScalableVector() || OpVT.getVectorElementType() != MVT::i1) in LowerPredReductionToSVE()
[all …]
H A DAArch64ISelLowering.h872 bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1169 EVT OpVT = OpI1.getValueType(); in ppHoistZextI1() local
1170 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) in ppHoistZextI1()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4674 MVT OpVT = ScalarOp.getSimpleValueType(); in lowerVectorIntrinsicScalars() local
4678 if (!OpVT.isScalarInteger() || OpVT == XLenVT) in lowerVectorIntrinsicScalars()
4682 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicScalars()
4703 assert(XLenVT == MVT::i32 && OpVT == MVT::i64 && in lowerVectorIntrinsicScalars()
6195 MVT OpVT = V.getSimpleValueType(); in lowerVPOp() local
6196 MVT ContainerVT = getContainerForFixedLengthVector(OpVT); in lowerVPOp()
6197 assert(useRVVForFixedLengthVectorVT(OpVT) && in lowerVPOp()
6883 EVT OpVT = Op0.getValueType(); in ReplaceNodeResults() local
8181 EVT OpVT = N0.getValueType(); in performSETCCCombine() local
8183 if (OpVT != MVT::i64 || !Subtarget.is64Bit()) in performSETCCCombine()
[all …]
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp2545 MVT::SimpleValueType OpVT = Int->IS.ParamVTs[i]; in ApplyTypeConstraints() local
2547 MadeChange |= getChild(i+1)->UpdateNodeType(0, OpVT, TP); in ApplyTypeConstraints()

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