| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | BreakFalseDeps.cpp | 136 const TargetRegisterClass *OpRC = in pickBestRegisterForUndef() local
143 !OpRC->contains(CurrMO.getReg())) in pickBestRegisterForUndef()
155 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| H A D | MachineInstr.cpp | 904 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect() local
910 if (OpRC) in getRegClassConstraintEffect()
911 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
914 } else if (OpRC) in getRegClassConstraintEffect()
915 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
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| H A D | RegAllocFast.cpp | 1086 const TargetRegisterClass *OpRC = MRI->getRegClass(Reg); in addRegClassDefCounts() local
1091 if (OpRC->hasSubClassEq(IdxRC)) in addRegClassDefCounts()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 1661 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr() local
1662 Register TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1669 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1683 Register VBStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
1703 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1704 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1705 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1707 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
1708 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
1713 Register VStateReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr()
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 315 const TargetRegisterClass *OpRC = nullptr; in AddRegisterOperand() local
317 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); in AddRegisterOperand()
319 if (OpRC) { in AddRegisterOperand()
328 = MRI->constrainRegClass(VReg, OpRC, MinNumRegs); in AddRegisterOperand()
330 OpRC = TRI->getAllocatableClass(OpRC); in AddRegisterOperand()
331 assert(OpRC && "Constraints cannot be fulfilled for allocation"); in AddRegisterOperand()
332 Register NewVReg = MRI->createVirtualRegister(OpRC); in AddRegisterOperand()
391 const TargetRegisterClass *OpRC = in AddOperand() local
398 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) { in AddOperand()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 112 const TargetRegisterClass *OpRC = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
118 if (OpRC) { in constrainOperandRegClass()
124 OpRC, TRI.getConstrainedRegClassForOperand(RegMO, MRI))) in constrainOperandRegClass()
125 OpRC = SubRC; in constrainOperandRegClass()
127 OpRC = TRI.getAllocatableClass(OpRC); in constrainOperandRegClass()
130 if (!OpRC) { in constrainOperandRegClass()
146 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 826 const TargetRegisterClass *OpRC = in processPHINode() local
828 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
829 OpRC != &AMDGPU::VS_64RegClass) { in processPHINode()
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| H A D | SIFoldOperands.cpp | 1555 const TargetRegisterClass *OpRC = in tryFoldRegSequence() local
1557 if (!OpRC || !TRI->isVectorSuperClass(OpRC)) in tryFoldRegSequence()
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| H A D | SIInstrInfo.cpp | 5437 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand() local
5441 if (DstRC == OpRC) in legalizeGenericOperand()
5750 const TargetRegisterClass *OpRC = in legalizeOperands() local
5752 if (RI.hasVectorRegisters(OpRC)) { in legalizeOperands()
5753 VRC = OpRC; in legalizeOperands()
5755 SRC = OpRC; in legalizeOperands()
5812 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg()); in legalizeOperands() local
5813 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC); in legalizeOperands()
5814 if (VRC == OpRC) in legalizeOperands()
7295 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1911 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF); in validateReg() local
1913 return OpRC->hasSubClassEq(RRC); in validateReg()
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