| /llvm-project-15.0.7/llvm/unittests/CodeGen/ |
| H A D | SelectionDAGAddressAnalysisTest.cpp | 161 TypeSize Offset1 = SubVecVT.getStoreSize(); in TEST_F() local 163 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F() 167 PtrInfo.getWithOffset(Offset1)); in TEST_F() 192 TypeSize Offset1 = SubVecVT.getStoreSize(); in TEST_F() local 193 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F() 286 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); in TEST_F() local 288 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F() 292 PtrInfo.getWithOffset(Offset1)); in TEST_F() 327 TypeSize Offset1 = SubFixedVecVT2xi8.getStoreSize(); in TEST_F() local 329 SDValue Index1 = DAG->getMemBasePlusOffset(FIPtr, Offset1, Loc); in TEST_F() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMHazardRecognizer.cpp | 205 int64_t Offset1 = 0; in getHazardType() local 211 Ptr1 = GetPointerBaseWithConstantOffset(BaseVal1, Offset1, DL, true); in getHazardType() 213 return CheckOffsets(Offset0, Offset1); in getHazardType() 223 Offset1 = MF.getFrameInfo().getObjectOffset(FS1->getFrameIndex()); in getHazardType() 224 return CheckOffsets(Offset0, Offset1); in getHazardType()
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| H A D | ARMBaseInstrInfo.h | 246 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 258 int64_t Offset1, int64_t Offset2,
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| /llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/ |
| H A D | DWARFListTableTest.cpp | 97 Optional<uint64_t> Offset1 = Header.getOffsetEntry(Extractor, 1); in TEST() local 98 EXPECT_FALSE(!!Offset1); in TEST()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.h | 156 bool isDSOffset2Legal(SDValue Base, unsigned Offset0, unsigned Offset1, 160 SDValue &Offset1) const; 162 SDValue &Offset1) const; 164 SDValue &Offset1, unsigned Size) const;
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| H A D | AMDGPUISelDAGToDAG.cpp | 1140 unsigned Offset1, in isDSOffset2Legal() argument 1142 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal() 1144 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal() 1159 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned() 1160 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 4); in SelectDS64Bit4ByteAligned() 1165 SDValue &Offset1) const { in SelectDS128Bit8ByteAligned() 1166 return SelectDSReadWrite2(Addr, Base, Offset0, Offset1, 8); in SelectDS128Bit8ByteAligned() 1170 SDValue &Offset0, SDValue &Offset1, in SelectDSReadWrite2() argument 1185 Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8); in SelectDSReadWrite2() 1236 Offset1 = CurDAG->getTargetConstant(OffsetValue1 / Size, DL, MVT::i8); in SelectDSReadWrite2() [all …]
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| H A D | AMDGPUInstructionSelector.h | 238 bool isDSOffset2Legal(Register Base, int64_t Offset0, int64_t Offset1,
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| H A D | SIInstrInfo.h | 192 int64_t &Offset1, 206 int64_t Offset1, unsigned NumLoads) const override;
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| H A D | SIInstrInfo.cpp | 177 int64_t &Offset1) const { in areLoadsFromSameBasePtr() 213 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue(); in areLoadsFromSameBasePtr() 245 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr() 278 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr() 336 unsigned Offset1 = Offset1Op->getImm(); in getMemOperandsWithOffsetWidth() local 337 if (Offset0 + 1 != Offset1) in getMemOperandsWithOffsetWidth() 528 int64_t Offset0, int64_t Offset1, in shouldScheduleLoadsNear() argument 530 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear() 536 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear() 3140 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local [all …]
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| H A D | AMDGPUInstructionSelector.cpp | 1347 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (Instruction << 4); in selectDSOrderedIntrinsic() local 1350 Offset1 |= (CountDw - 1) << 6; in selectDSOrderedIntrinsic() 1353 Offset1 |= ShaderType << 2; in selectDSOrderedIntrinsic() 1355 unsigned Offset = Offset0 | (Offset1 << 8); in selectDSOrderedIntrinsic() 4343 int64_t Offset1, in isDSOffset2Legal() argument 4345 if (Offset0 % Size != 0 || Offset1 % Size != 0) in isDSOffset2Legal() 4347 if (!isUInt<8>(Offset0 / Size) || !isUInt<8>(Offset1 / Size)) in isDSOffset2Legal()
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| H A D | SILoadStoreOptimizer.cpp | 1961 uint64_t Offset1 = Src1->getImm(); in processBaseWithConstOffset() local 1968 Addr.Offset = (*Offset0P & 0x00000000ffffffff) | (Offset1 << 32); in processBaseWithConstOffset()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 242 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local 243 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads() 244 Offset1 == Offset2 || in ClusterNeighboringLoads() 250 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads() 251 Offsets.push_back(Offset1); in ClusterNeighboringLoads() 254 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 423 int64_t Offset1; in apply() local 425 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply() 431 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 400 int64_t Offset1, Offset2; in ConsecutiveInstr() local 401 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr() 409 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /llvm-project-15.0.7/llvm/test/CodeGen/SPARC/ |
| H A D | 64abi.ll | 476 ; HARD-DAG: std %f6, [%sp+[[Offset1:[0-9]+]]] 478 ; HARD-DAG: ldx [%sp+[[Offset1]]], %o3 494 ; HARD: st %f0, [%fp+[[Offset1:[0-9]+]]] 499 ; HARD: ld [%fp+[[Offset1]]], %f1
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 430 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 448 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | ConstraintElimination.cpp | 324 int64_t Offset1 = ADec[0].first; in getConstraint() local 326 Offset1 *= -1; in getConstraint() 362 if (AddOverflow(Offset1, Offset2, OffsetSum)) in getConstraint()
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| H A D | SeparateConstOffsetFromGEP.cpp | 1351 Value *Offset1 = First->getOperand(1); in swapGEPOperand() local 1354 Second->setOperand(1, Offset1); in swapGEPOperand()
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| /llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | ContainerModeling.cpp | 125 SymbolRef Offset1, 959 SymbolRef Offset1, in invalidateIteratorPositions() argument 964 return compare(State, Pos.getOffset(), Offset1, Opc1) && in invalidateIteratorPositions()
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| /llvm-project-15.0.7/llvm/tools/llvm-profgen/ |
| H A D | ProfiledBinary.cpp | 236 uint64_t Offset1 = virtualAddrToOffset(Address1); in inlineContextEqual() local 238 const SampleContextFrameVector &Context1 = getFrameLocationStack(Offset1); in inlineContextEqual()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1314 int64_t &Offset1, in areLoadsFromSameBasePtr() argument 1328 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3270 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument 3287 ObjectOffset1 += Offset1; in shouldClusterFI() 3337 int64_t Offset1 = FirstLdSt.getOperand(2).getImm(); in shouldClusterMemOps() local 3338 if (hasUnscaledLdStOffset(FirstOpc) && !scaleOffset(FirstOpc, Offset1)) in shouldClusterMemOps() 3346 if (Offset1 > 63 || Offset1 < -64) in shouldClusterMemOps() 3352 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps() 3357 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps() 3361 assert(Offset1 <= Offset2 && "Caller should have ordered offsets."); in shouldClusterMemOps() 3363 return Offset1 + 1 == Offset2; in shouldClusterMemOps()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 775 int64_t Offset1, Offset2; in addLoopCarriedDependences() local 777 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, in addLoopCarriedDependences() 783 (int)Offset1 < (int)Offset2) { in addLoopCarriedDependences()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 1153 const APInt *Offset1 = nullptr, *Offset2 = nullptr; in foldAndOrOfICmpsUsingRanges() local 1156 if (match(V1, m_Add(m_Value(X), m_APInt(Offset1)))) in foldAndOrOfICmpsUsingRanges() 1167 if (Offset1) in foldAndOrOfICmpsUsingRanges() 1168 CR1 = CR1.subtract(*Offset1); in foldAndOrOfICmpsUsingRanges()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ConstantFolding.cpp | 1308 APInt Offset1(IndexWidth, 0); in ConstantFoldCompareInstOperands() local 1310 Ops1->stripAndAccumulateInBoundsConstantOffsets(DL, Offset1); in ConstantFoldCompareInstOperands() 1315 ConstantInt::get(CE0->getContext(), Offset1)); in ConstantFoldCompareInstOperands()
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