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Searched refs:NewVT (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp219 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
232 NewVT, 2*OldElts), in ExpandRes_EXTRACT_VECTOR_ELT()
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
376 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
396 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp312 NewVT, Op); in ScalarizeVecRes_BITCAST()
2566 [&Output, &DAG = DAG, NewVT]() { Output = DAG.getUNDEF(NewVT); }, in SplitVecRes_VECTOR_SHUFFLE()
5726 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST()
6364 Optional<EVT> NewVT = FirstVT; in GenWidenVectorLoads() local
6373 if (!NewVT) in GenWidenVectorLoads()
6377 MemVTs.push_back(*NewVT); in GenWidenVectorLoads()
6587 Optional<EVT> NewVT = in GenWidenVectorStores() local
6589 if (!NewVT) in GenWidenVectorStores()
6591 MemVTs.push_back({*NewVT, 0}); in GenWidenVectorStores()
6601 EVT NewVT = Pair.first; in GenWidenVectorStores() local
[all …]
H A DDAGCombiner.cpp4697 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
4701 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
4767 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
4771 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
4896 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitSMUL_LOHI()
4901 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
4946 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitUMUL_LOHI()
4951 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
5136 NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, in PerformMinMaxFpToSatCombine()
5172 NewVT = EVT::getVectorVT(*DAG.getContext(), NewVT, in PerformUMinFpToSatCombine()
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H A DTargetLowering.cpp234 EVT NewVT = VT; in findOptimalMemOpLowering() local
239 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in findOptimalMemOpLowering()
240 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
241 isSafeMemOpType(NewVT.getSimpleVT())) in findOptimalMemOpLowering()
243 else if (NewVT == MVT::i64 && in findOptimalMemOpLowering()
247 NewVT = MVT::f64; in findOptimalMemOpLowering()
254 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in findOptimalMemOpLowering()
255 if (NewVT == MVT::i8) in findOptimalMemOpLowering()
257 } while (!isSafeMemOpType(NewVT.getSimpleVT())); in findOptimalMemOpLowering()
259 NewVTSize = NewVT.getSizeInBits() / 8; in findOptimalMemOpLowering()
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H A DLegalizeDAG.cpp3055 EVT NewVT = in ExpandNode() local
3058 assert(NewVT.bitsEq(VT)); in ExpandNode()
3061 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3062 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
3066 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
3082 VT = NewVT; in ExpandNode()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1123 MVT NewVT = MVT::getVectorVT(EltTy, EC); in getVectorTypeBreakdownMVT() local
1124 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
1125 NewVT = EltTy; in getVectorTypeBreakdownMVT()
1126 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1134 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1601 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); in getVectorTypeBreakdown() local
1602 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1603 NewVT = EltTy; in getVectorTypeBreakdown()
1604 IntermediateVT = NewVT; in getVectorTypeBreakdown()
1606 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown()
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/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h129 EVT NewVT) const override { in shouldReduceLoadWidth() argument
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp391 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]); in lowerReturn() local
392 if (EVT(NewVT) != SplitEVTs[i]) { in lowerReturn()
399 LLT NewLLT(NewVT); in lowerReturn()
401 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx); in lowerReturn()
404 if (NewVT.isVector()) { in lowerReturn()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp573 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT); in determineAssignments() local
582 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
613 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i], in determineAssignments()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h320 EVT NewVT) const override;
H A DHexagonISelLowering.cpp3600 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()
3602 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp634 EVT NewVT) const { in shouldReduceLoadWidth()
636 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
639 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
2893 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
2896 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
2944 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
2950 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
H A DR600ISelLowering.cpp1678 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1681 NewVT = VT; in constBufferLoad()
1684 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp5046 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
5047 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
5048 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
5050 EVT SelectVT = NewVT; in ReplaceNodeResults()
5051 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
5060 if (NewVT != SelectVT) in ReplaceNodeResults()
5061 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
6566 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local
6570 ResultTypes[0] = NewVT; in lowerImage()
10724 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
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H A DAMDGPUISelDAGToDAG.cpp691 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
692 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h591 EVT NewVT) const override;
H A DAArch64ISelLowering.cpp3745 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
3755 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
4182 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
4184 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
10439 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) { in tryWidenMaskForShuffle()
10440 V0 = DAG.getBitcast(NewVT, V0); in tryWidenMaskForShuffle()
10441 V1 = DAG.getBitcast(NewVT, V1); in tryWidenMaskForShuffle()
15505 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); in tryExtendDUPToExtractHigh() local
15506 N = DAG.getNode(N->getOpcode(), DL, NewVT, N->ops()); in tryExtendDUPToExtractHigh()
21765 EVT NewVT = in LowerFixedLengthVECTOR_SHUFFLEToSVE() local
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1343 EVT NewVT) const override;
H A DX86ISelLowering.cpp10154 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
10156 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
10157 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
14175 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
14176 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
19461 V1 = DAG.getBitcast(NewVT, V1); in lowerVECTOR_SHUFFLE()
19462 V2 = DAG.getBitcast(NewVT, V2); in lowerVECTOR_SHUFFLE()
28680 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems); in LowerVectorCTLZ_AVX512CDI() local
28681 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) && in LowerVectorCTLZ_AVX512CDI()
31422 Op = DAG.getNode(ISD::CTPOP, DL, NewVT, Op); in LowerVectorCTPOP()
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/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2004 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
2007 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
2008 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/llvm-project-15.0.7/clang/lib/AST/
H A DDecl.cpp2633 auto *NewVT = VarTemplate->getInstantiatedFromMemberTemplate(); in getTemplateInstantiationPattern() local
2634 if (!NewVT) in getTemplateInstantiationPattern()
2636 VarTemplate = NewVT; in getTemplateInstantiationPattern()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1604 EVT NewVT) const { in shouldReduceLoadWidth() argument
1607 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3023 MVT NewVT = in expandUnalignedRVVLoad() local
3025 assert(NewVT.isValid() && in expandUnalignedRVVLoad()
3027 SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(), in expandUnalignedRVVLoad()
3054 MVT NewVT = in expandUnalignedRVVStore() local
3056 assert(NewVT.isValid() && in expandUnalignedRVVStore()
3058 StoredVal = DAG.getBitcast(NewVT, StoredVal); in expandUnalignedRVVStore()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp8476 EVT NewVT = getVectorTyFromPredicateVector(VT); in PromoteMVEPredVector() local
8494 return DAG.getNode(ISD::BITCAST, dl, NewVT, PredAsVector); in PromoteMVEPredVector()
8525 EVT NewVT = PredAsVector.getValueType(); in LowerVECTOR_SHUFFLE_i1() local
8528 SDValue Shuffled = DAG.getVectorShuffle(NewVT, dl, PredAsVector, in LowerVECTOR_SHUFFLE_i1()
8529 DAG.getUNDEF(NewVT), ShuffleMask); in LowerVECTOR_SHUFFLE_i1()
9025 EVT NewVT = NewV.getValueType(); in LowerCONCAT_VECTORS_i1() local
9027 for (unsigned i = 0, e = NewVT.getVectorNumElements(); i < e; i++, j++) { in LowerCONCAT_VECTORS_i1()
9360 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local
9362 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14082 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation() local
14083 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops); in combineElementTruncationToVectorTruncation()