| /llvm-project-15.0.7/llvm/lib/FuzzMutate/ |
| H A D | RandomIRBuilder.cpp | 60 auto *NewLoad = new LoadInst(AccessTy, Ptr, "L", &*IP); in newSource() local 63 if (Pred.matches(Srcs, NewLoad)) in newSource() 64 RS.sample(NewLoad, RS.totalWeight()); in newSource() 66 NewLoad->eraseFromParent(); in newSource()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | VNCoercion.cpp | 486 LoadInst *NewLoad = Builder.CreateLoad(DestTy, PtrVal); in getLoadValueForLoad() local 487 NewLoad->takeName(SrcVal); in getLoadValueForLoad() 488 NewLoad->setAlignment(SrcVal->getAlign()); in getLoadValueForLoad() 491 LLVM_DEBUG(dbgs() << "TO: " << *NewLoad << "\n"); in getLoadValueForLoad() 495 Value *RV = NewLoad; in getLoadValueForLoad() 501 SrcVal = NewLoad; in getLoadValueForLoad()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineLoadStoreAlloca.cpp | 473 LoadInst *NewLoad = Builder.CreateAlignedLoad( in combineLoadToNewType() local 475 NewLoad->setAtomic(LI.getOrdering(), LI.getSyncScopeID()); in combineLoadToNewType() 476 copyMetadataForLoad(*NewLoad, LI); in combineLoadToNewType() 477 return NewLoad; in combineLoadToNewType() 610 LoadInst *NewLoad = IC.combineLoadToNewType(LI, CI->getDestTy()); in combineLoadToOperationType() local 611 CI->replaceAllUsesWith(NewLoad); in combineLoadToOperationType() 640 NewLoad->setAAMetadata(LI.getAAMetadata()); in unpackLoadToAggregate() 642 UndefValue::get(T), NewLoad, 0, Name)); in unpackLoadToAggregate() 681 LoadInst *NewLoad = IC.combineLoadToNewType(LI, ET, ".unpack"); in unpackLoadToAggregate() local 682 NewLoad->setAAMetadata(LI.getAAMetadata()); in unpackLoadToAggregate() [all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | ExpandVectorPredication.cpp | 432 LoadInst *NewLoad = in expandPredicationInMemoryIntrinsic() local 435 NewLoad->setAlignment(AlignOpt.value()); in expandPredicationInMemoryIntrinsic() 436 NewMemoryInst = NewLoad; in expandPredicationInMemoryIntrinsic()
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| /llvm-project-15.0.7/polly/lib/CodeGen/ |
| H A D | BlockGenerators.cpp | 369 Value *NewLoad = generateArrayLoad(Stmt, Load, BBMap, LTS, NewAccesses); in copyInstruction() local 372 BBMap[Load] = NewLoad; in copyInstruction() 1138 Value *NewLoad; in generateLoad() local 1140 NewLoad = generateStrideZeroLoad(Stmt, Load, ScalarMaps[0], NewAccesses); in generateLoad() 1142 NewLoad = generateStrideOneLoad(Stmt, Load, ScalarMaps, NewAccesses); in generateLoad() 1144 NewLoad = generateStrideOneLoad(Stmt, Load, ScalarMaps, NewAccesses, true); in generateLoad() 1146 NewLoad = generateUnknownStrideLoad(Stmt, Load, ScalarMaps, NewAccesses); in generateLoad() 1148 VectorMap[Load] = NewLoad; in generateLoad()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | GVN.cpp | 1339 auto *NewLoad = in eliminatePartiallyRedundantLoad() local 1343 NewLoad->setDebugLoc(Load->getDebugLoc()); in eliminatePartiallyRedundantLoad() 1353 NewLoad, DefiningAcc, NewLoad->getParent(), in eliminatePartiallyRedundantLoad() 1364 NewLoad->setAAMetadata(Tags); in eliminatePartiallyRedundantLoad() 1367 NewLoad->setMetadata(LLVMContext::MD_invariant_load, MD); in eliminatePartiallyRedundantLoad() 1369 NewLoad->setMetadata(LLVMContext::MD_invariant_group, InvGroupMD); in eliminatePartiallyRedundantLoad() 1371 NewLoad->setMetadata(LLVMContext::MD_range, RangeMD); in eliminatePartiallyRedundantLoad() 1375 NewLoad->setMetadata(LLVMContext::MD_access_group, AccessMD); in eliminatePartiallyRedundantLoad() 1385 AvailableValueInBlock::get(UnavailableBlock, NewLoad)); in eliminatePartiallyRedundantLoad() 1387 LLVM_DEBUG(dbgs() << "GVN INSERTED " << *NewLoad << '\n'); in eliminatePartiallyRedundantLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86AvoidStoreForwardingBlocks.cpp | 393 MachineInstr *NewLoad = in buildCopy() local 404 getBaseOperand(NewLoad).setIsKill(false); in buildCopy() 405 LLVM_DEBUG(NewLoad->dump()); in buildCopy()
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| H A D | X86InterleavedAccess.cpp | 224 Instruction *NewLoad = in decompose() local 226 DecomposedVectors.push_back(NewLoad); in decompose()
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| H A D | X86ISelLowering.cpp | 32014 SDValue NewLoad = DAG.getMaskedLoad( in LowerMLOAD() local 32020 SDValue Select = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD() 32021 return DAG.getMergeValues({ Select, NewLoad.getValue(1) }, dl); in LowerMLOAD() 32051 SDValue NewLoad = DAG.getMaskedLoad( in LowerMLOAD() local 32057 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, NewLoad.getValue(0), in LowerMLOAD() 32059 SDValue RetOps[] = {Extract, NewLoad.getValue(1)}; in LowerMLOAD()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 1057 auto *NewLoad = cast<LoadInst>(Builder.CreateLoad( in scalarizeLoadExtract() local 1062 NewLoad->setAlignment(ScalarOpAlignment); in scalarizeLoadExtract() 1064 replaceValue(*EI, *NewLoad); in scalarizeLoadExtract()
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| H A D | LoopVectorize.cpp | 2613 Instruction *NewLoad; in vectorizeInterleaveGroup() local 2629 NewLoad = in vectorizeInterleaveGroup() 2634 NewLoad = Builder.CreateAlignedLoad(VecTy, AddrParts[Part], in vectorizeInterleaveGroup() 2636 Group->addMetadata(NewLoad); in vectorizeInterleaveGroup() 2637 NewLoads.push_back(NewLoad); in vectorizeInterleaveGroup()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1406 SDValue NewLoad; in ExpandExtractFromVectorThroughStack() local 1415 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, in ExpandExtractFromVectorThroughStack() 1419 NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, in ExpandExtractFromVectorThroughStack() 1425 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1)); in ExpandExtractFromVectorThroughStack() 1429 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(), in ExpandExtractFromVectorThroughStack() 1430 NewLoad->op_end()); in ExpandExtractFromVectorThroughStack() 1432 NewLoad = in ExpandExtractFromVectorThroughStack() 1433 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0); in ExpandExtractFromVectorThroughStack() 1434 return NewLoad; in ExpandExtractFromVectorThroughStack()
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| H A D | DAGCombiner.cpp | 5922 assert(NewLoad && in BackwardsPropagateMask() 5924 CombineTo(Load, NewLoad, NewLoad.getValue(1)); in BackwardsPropagateMask() 6344 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), in visitAND() 6348 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); in visitAND() 8282 SDValue NewLoad = in MatchLoadCombine() local 8292 return NewLoad; in MatchLoadCombine() 8299 : NewLoad; in MatchLoadCombine() 11807 return NewLoad; in tryToFoldExtOfMaskedLoad() 13353 return NewLoad; in visitTRUNCATE() 16854 (void)NewLoad; in visitLOAD() [all …]
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| H A D | LegalizeVectorTypes.cpp | 4876 SDValue NewLoad = in WidenVecRes_LOAD() local 4883 ReplaceValueWith(SDValue(N, 1), NewLoad.getValue(1)); in WidenVecRes_LOAD() 4885 return NewLoad; in WidenVecRes_LOAD()
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| H A D | TargetLowering.cpp | 4346 SDValue NewLoad = in SimplifySetCC() local 4351 DAG.getNode(ISD::AND, dl, newVT, NewLoad, in SimplifySetCC()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1135 auto NewLoad = MIRBuilder.buildLoad(NewTy, MI.getOperand(1), MMO); in legalizeLoadStore() local 1136 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1363 SDValue NewLoad = DAG.getExtLoad( in LowerLOAD() local 1366 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
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| H A D | AMDGPUISelLowering.cpp | 2895 SDValue NewLoad in performLoadCombine() local 2899 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine() 2900 DCI.CombineTo(N, BC, NewLoad.getValue(1)); in performLoadCombine()
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| H A D | SIISelLowering.cpp | 8567 SDValue NewLoad = DAG.getLoad( in widenLoad() local 8580 SDValue Cvt = NewLoad; in widenLoad() 8582 Cvt = DAG.getNode(ISD::SIGN_EXTEND_INREG, SL, MVT::i32, NewLoad, in widenLoad() 8586 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad() 8604 return DAG.getMergeValues({ Cvt, NewLoad.getValue(1) }, SL); in widenLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10118 SDValue NewLoad = DAG.getMaskedLoad( in LowerMLOAD() local 10122 SDValue Combo = NewLoad; in LowerMLOAD() 10128 return DAG.getMergeValues({Combo, NewLoad.getValue(1)}, dl); in LowerMLOAD() 17537 SDValue NewLoad = in PerformSplittingToWideningLoad() local 17541 Loads.push_back(NewLoad); in PerformSplittingToWideningLoad() 17542 Chains.push_back(SDValue(NewLoad.getNode(), 1)); in PerformSplittingToWideningLoad() 17605 return NewLoad; in PerformExtendCombine() 17614 return NewLoad; in PerformFPExtendCombine() 18461 SDValue NewLoad = in PerformSplittingMVEEXTToWideningLoad() local 18465 Loads.push_back(NewLoad); in PerformSplittingMVEEXTToWideningLoad() [all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2959 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad() local 2960 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad() 2962 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); in lowerLoad() local 2965 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15242 SDValue NewLoad = in performConcatVectorsCombine() local 15246 Ops.push_back(NewLoad); in performConcatVectorsCombine() 17257 SDValue NewLoad = DAG.getMaskedLoad( in performUnpackCombine() local 17262 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), NewLoad.getValue(1)); in performUnpackCombine() 17264 return NewLoad; in performUnpackCombine() 20998 SDValue NewLoad = DAG.getMaskedLoad( in LowerFixedLengthVectorLoadToSVE() local 21003 SDValue Result = NewLoad; in LowerFixedLengthVectorLoadToSVE() 21014 SDValue MergedValues[2] = {Result, NewLoad.getValue(1)}; in LowerFixedLengthVectorLoadToSVE() 21062 SDValue NewLoad = DAG.getMaskedLoad( in LowerFixedLengthVectorMLoadToSVE() local 21067 SDValue Result = NewLoad; in LowerFixedLengthVectorMLoadToSVE() [all …]
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2650 SDValue NewLoad = DAG.getMemIntrinsicNode( in lowerVECTOR_SHUFFLE() local 2654 DAG.makeEquivalentMemoryOrdering(Ld, NewLoad); in lowerVECTOR_SHUFFLE() 2655 return convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerVECTOR_SHUFFLE() 5854 SDValue NewLoad = in lowerFixedLengthVectorLoadToRVV() local 5858 SDValue Result = convertFromScalableVector(VT, NewLoad, DAG, Subtarget); in lowerFixedLengthVectorLoadToRVV() 5859 return DAG.getMergeValues({Result, NewLoad.getValue(1)}, DL); in lowerFixedLengthVectorLoadToRVV()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3518 SDValue NewLoad = DAG.getLoad(ResVT, DL, LoadN->getChain(), in lowerBITCAST() local 3521 DAG.ReplaceAllUsesOfValueWith(SDValue(LoadN, 1), NewLoad.getValue(1)); in lowerBITCAST() 3522 return NewLoad; in lowerBITCAST()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11099 SDValue NewLoad[2]; in LowerFP_EXTEND() local 11108 NewLoad[i] = DAG.getMemIntrinsicNode( in LowerFP_EXTEND() 11113 DAG.getNode(Op0.getOpcode(), SDLoc(Op0), MVT::v4f32, NewLoad[0], in LowerFP_EXTEND() 11114 NewLoad[1], Op0.getNode()->getFlags()); in LowerFP_EXTEND()
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