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Searched refs:Mask1 (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZTDC.cpp293 int Mask0, Mask1; in convertLogicOp() local
296 std::tie(Op1, Mask1, Worthy1) = ConvertedInsts[cast<Instruction>(I.getOperand(1))]; in convertLogicOp()
302 Mask = Mask0 & Mask1; in convertLogicOp()
305 Mask = Mask0 | Mask1; in convertLogicOp()
308 Mask = Mask0 ^ Mask1; in convertLogicOp()
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dmips-options-sec.test13 # CHECK-NEXT: Co-Proc Mask1: 0xCCBBAA99
21 # CHECK-NEXT: Co-Proc Mask1: 0x0
41 # NAME-ERR-FOUND-NEXT: Co-Proc Mask1: 0xCCBBAA99
49 # NAME-ERR-FOUND-NEXT: Co-Proc Mask1: 0x0
134 # KIND-NEXT: Co-Proc Mask1: 0x0
H A Dmips-reginfo.test11 # OPTIONS-NEXT: Co-Proc Mask1: 0xCCBBAA99
/llvm-project-15.0.7/llvm/unittests/ADT/
H A DBitVectorTest.cpp785 const uint32_t Mask1[] = { 0x80000000, 6, 5 }; in TYPED_TEST() local
788 A.setBitsInMask(Mask1, 1); in TYPED_TEST()
793 A.setBitsInMask(Mask1, 1); in TYPED_TEST()
799 A.setBitsInMask(Mask1, 1); in TYPED_TEST()
801 A.setBitsInMask(Mask1, 2); in TYPED_TEST()
805 A.setBitsInMask(Mask1, 2); in TYPED_TEST()
809 A.setBitsInMask(Mask1, 3); in TYPED_TEST()
812 A.setBitsNotInMask(Mask1, 1); in TYPED_TEST()
815 A.setBitsNotInMask(Mask1, 3); in TYPED_TEST()
823 A.setBitsNotInMask(Mask1, 3); in TYPED_TEST()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp241 VPValue *Mask1 = getPredicatedMask(Region1); in mergeReplicateRegions() local
243 if (!Mask1 || Mask1 != Mask2) in mergeReplicateRegions()
250 assert(Mask1 && Mask2 && "both region must have conditions"); in mergeReplicateRegions()
/llvm-project-15.0.7/lld/test/ELF/
H A Dmips-reginfo.s22 # CHECK-NEXT: Co-Proc Mask1: 0x0
H A Dmips-options.s39 # CHECK-NEXT: Co-Proc Mask1: 0x0
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp874 auto IsSubmask = [](const Value *Mask0, const Value *Mask1) { in isNonTargetIntrinsicMatch() argument
876 if (Mask0 == Mask1) in isNonTargetIntrinsicMatch()
878 if (isa<UndefValue>(Mask0) || isa<UndefValue>(Mask1)) in isNonTargetIntrinsicMatch()
881 auto *Vec1 = dyn_cast<ConstantVector>(Mask1); in isNonTargetIntrinsicMatch()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSystemRegister.td45 // Mask1 Mask2 Mask3 Enc12, Name
H A DARMISelLowering.cpp6043 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32); in LowerFCOPYSIGN() local
6045 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); in LowerFCOPYSIGN()
/llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2054 uint64_t Mask1 = computeKnownBits(Mask, 0, II).One.getZExtValue(); in visitCallInst() local
2056 uint64_t C = Bytes1 & Mask1; in visitCallInst()
H A DInstCombineCompares.cpp3274 APInt Mask1 = IsTrailing ? APInt::getLowBitsSet(BitWidth, Num + 1) in foldICmpEqIntrinsicWithConstant() local
3279 return new ICmpInst(Pred, Builder.CreateAnd(II->getArgOperand(0), Mask1), in foldICmpEqIntrinsicWithConstant()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6759 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1)); in matchBSwapHWordOrAndAnd() local
6760 if (!Mask0 || !Mask1) in matchBSwapHWordOrAndAnd()
6763 Mask1->getAPIntValue() != 0x00ff00ff) in matchBSwapHWordOrAndAnd()
21889 SmallVector<int, 16> Mask1(HalfNumElts, -1); in foldShuffleOfConcatUndefs() local
21900 Mask1[i - HalfNumElts] = M; in foldShuffleOfConcatUndefs()
21908 !TLI.isShuffleMaskLegal(Mask1, HalfVT)) in foldShuffleOfConcatUndefs()
21916 SDValue Shuf1 = DAG.getVectorShuffle(HalfVT, DL, X, Y, Mask1); in foldShuffleOfConcatUndefs()
H A DTargetLowering.cpp8151 APInt Mask1 = APInt::getSplat(Sz, APInt(8, 0x55)); in expandBITREVERSE() local
8172 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
8173 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(Mask1, dl, VT)); in expandBITREVERSE()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5964 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); in lowerU64ToF32BitOps() local
5965 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8265 SmallVector<int, 64> Mask0, Mask1; in getFauxShuffleMask() local
8267 narrowShuffleMaskElts(MaskSize / SrcMask1.size(), SrcMask1, Mask1); in getFauxShuffleMask()
8273 if (Mask0[i] == SM_SentinelZero && Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
8275 else if (Mask1[i] == SM_SentinelZero) in getFauxShuffleMask()
46782 SmallVector<int> Mask0, Mask1, ScaledMask0, ScaledMask1; in combineHorizOpWithShuffle() local
46788 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
46789 scaleShuffleElements(Mask1, 2, ScaledMask1) && in combineHorizOpWithShuffle()
46836 SmallVector<int> Mask0, Mask1; in combineHorizOpWithShuffle() local
46840 getTargetShuffleInputs(BC1, Ops1, Mask1, DAG) && !isAnyZero(Mask1) && in combineHorizOpWithShuffle()
46847 scaleShuffleElements(Mask1, 2, ScaledMask1)) { in combineHorizOpWithShuffle()
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGBuiltin.cpp15443 Value *Mask1 = Builder.CreateCall(Lvs, Op0, "mask1"); in EmitPPCBuiltinExpr() local
15447 Value *AllElts = Builder.CreateCall(Vperm, {Op0, Op1, Mask1}, "shuffle1"); in EmitPPCBuiltinExpr()