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/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Daix-vector-vararg-fixed-caller.ll29 ; 32BIT: [[LFD:%[0-9]+]]:f8rc = LFD 0, killed [[LWZtoc2]] :: (load (s64) from constant-pool)
35 ; 32BIT: [[LFD1:%[0-9]+]]:f8rc = LFD 0, killed [[LWZtoc3]] :: (load (s64) from constant-pool)
39 ; 32BIT: $f1 = COPY [[LFD]]
65 ; 64BIT: [[LFD:%[0-9]+]]:f8rc = LFD 0, killed [[LDtocCPT2]] :: (load (s64) from constant-pool)
67 ; 64BIT: [[LFD1:%[0-9]+]]:f8rc = LFD 0, killed [[LDtocCPT3]] :: (load (s64) from constant-pool)
76 ; 64BIT: $f1 = COPY [[LFD]]
H A Daix32-vector-vararg-fixed-callee.ll17 ; CHECK: [[LFD:%[0-9]+]]:f8rc = LFD 16, killed [[RLWINM]] :: (load (s64) from %ir.4, align 16)
19 ; CHECK: $f1 = COPY [[LFD]]
H A Daix-vec-arg-spills-callee.ll44 ; MIR32: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.2
45 ; MIR32: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.0
63 ; MIR64: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.2
64 ; MIR64: renamable $f{{[0-9]+}} = LFD 0, %fixed-stack.0
H A Daix64-vector-vararg-fixed-callee.ll24 ; CHECK: [[LFD:%[0-9]+]]:f8rc = LFD 16, killed [[RLDICR]] :: (load (s64) from %ir.4, align 16)
26 ; CHECK: $f1 = COPY [[LFD]]
H A Daix-csr-vector.ll94 ; MIR32-DAG: $f14 = LFD -144, $r1 :: (load (s64) from %fixed-stack.2, align 16)
95 ; MIR32-DAG: $f21 = LFD -88, $r1 :: (load (s64) from %fixed-stack.1)
96 ; MIR32-DAG: $f31 = LFD -8, $r1 :: (load (s64) from %fixed-stack.0)
123 ; MIR64-DAG: $f14 = LFD -144, $x1 :: (load (s64) from %fixed-stack.2, align 16)
124 ; MIR64-DAG: $f21 = LFD -88, $x1 :: (load (s64) from %fixed-stack.1)
125 ; MIR64-DAG: $f31 = LFD -8, $x1 :: (load (s64) from %fixed-stack.0)
H A Daix-csr.ll175 ; MIR64-DAG: $f31 = LFD 392, $x1 :: (load (s64) from %fixed-stack.0)
176 ; MIR64-DAG: $f21 = LFD 312, $x1 :: (load (s64) from %fixed-stack.1)
177 ; MIR64-DAG: $f19 = LFD 296, $x1 :: (load (s64) from %fixed-stack.2)
178 ; MIR64-DAG: $f14 = LFD 256, $x1 :: (load (s64) from %fixed-stack.3, align 16)
205 ; MIR32-DAG: $f31 = LFD 280, $r1 :: (load (s64) from %fixed-stack.0)
206 ; MIR32-DAG: $f21 = LFD 200, $r1 :: (load (s64) from %fixed-stack.1)
207 ; MIR32-DAG: $f19 = LFD 184, $r1 :: (load (s64) from %fixed-stack.2)
208 ; MIR32-DAG: $f14 = LFD 144, $r1 :: (load (s64) from %fixed-stack.3, align 16)
H A Daix-cc-abi.ll451 ; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from…
604 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG2]] :: (dereferenceable load (s64) fro…
614 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG2]] :: (dereferenceable load (s64) fro…
708 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from…
739 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from…
777 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from…
808 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from…
848 ; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) from…
881 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load (s64) from…
1197 ; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r[[REG]] :: (dereferenceable load (s64) fro…
[all …]
H A Dinstr-properties.ll6 ; CHECK-P8: %{{[0-9]+}}:f8rc = LFD target-flags(ppc-toc-lo) %const.0, %{{[0-9]+}}, implicit $x2 ::
H A Daix-dfltabi-rsrvd-reg.ll88 ; EXTABI-DAG: renamable $f0 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
93 ; EXTABI-DAG: renamable $f0 = LFD 0, renamable $x4 :: (volatile load (s64) from %ir.b, align 4)
96 ; EXTABI: renamable $f1 = LFD 0, killed renamable $x4 :: (volatile load (s64) from %ir.b, a…
H A Daix-csr-vector-extabi.ll171 ; MIR32-DAG: $f14 = LFD 304, $r1 :: (load (s64) from %fixed-stack.5, align 16)
172 ; MIR32-DAG: $f21 = LFD 360, $r1 :: (load (s64) from %fixed-stack.4)
173 ; MIR32-DAG: $f31 = LFD 440, $r1 :: (load (s64) from %fixed-stack.3)
236 ; MIR64-DAG: $f14 = LFD 400, $x1 :: (load (s64) from %fixed-stack.5, align 16)
237 ; MIR64-DAG: $f21 = LFD 456, $x1 :: (load (s64) from %fixed-stack.4)
238 ; MIR64-DAG: $f31 = LFD 536, $x1 :: (load (s64) from %fixed-stack.3)
H A Daix64-cc-abi-vaarg.ll232 ; 64BIT-DAG: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64))
235 ; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x6 :: (load (s64))
322 ; 64BIT-DAG: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64))
H A Dtoc-float.ll108 ; Access an element with an offset that doesn't fit in the displacement field of LFD.
H A Daix32-cc-abi-vaarg.ll381 ; 32BIT-DAG: renamable $f1 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
384 ; 32BIT-DAG: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
H A Daix-cc-byval.ll902 ; 32BIT-NEXT: renamable $f1 = LFD 16, %fixed-stack.0 :: (dereferenceable load (s64)
915 ; 64BIT-NEXT: renamable $f1 = LFD 16, %fixed-stack.0 :: (dereferenceable load (s64)
H A Dconvert-rr-to-ri-instrs.mir3013 ; CHECK: LFD -20, killed %6
3020 ; CHECK: LFD -20, killed %11
/llvm-project-15.0.7/lld/ELF/Arch/
H A DPPCInsns.def13 PCREL_OPT(LFD, PLFD, OPC_AND_RST);
H A DPPC64.cpp78 LFD = 0xc8000000, enumerator
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h138 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
146 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
154 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \
H A DPPCFastISel.cpp163 unsigned FP64LoadOpc = PPC::LFD);
514 bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD; in PPCEmitLoad()
567 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break; in PPCEmitLoad()
613 Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) in SelectLoad()
1040 unsigned LoadOpc = PPC::LFD; in PPCMoveToFPReg()
2019 Opc = ((VT == MVT::f32) ? PPC::LFS : PPC::LFD); in PPCMaterializeFP()
2366 Subtarget->hasSPE() ? PPC::EVLDD : PPC::LFD)) in tryToFoldLoadIntoMI()
H A DPPCPreEmitPeephole.cpp83 case PPC::LFD: in hasPCRelativeForm()
H A DPPCInstrInfo.cpp2946 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
4150 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
4271 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
H A DPPCRegisterInfo.cpp107 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
H A DP10InstrResources.td1286 DFLOADf32, DFLOADf64, LFD,
H A DP9InstrResources.td767 LFD
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/bugprone/
H A DEasilySwappableParametersCheck.cpp2300 if (const FunctionDecl *LFD = LTR.getUserDefinedConversionFunction()) in check() local
2301 diag(LFD->getLocation(), ConversionFunctionDiagText, in check()

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