1; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs -mcpu=pwr7 \
2; RUN:     -mattr=+altivec -stop-after=prologepilog < %s | \
3; RUN:   FileCheck --check-prefix=MIR32 %s
4
5; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
6; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
7; RUN:   FileCheck --check-prefix=ASM32 %s
8
9; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
10; RUN:     -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
11; RUN:   FileCheck --check-prefix=MIR64 %s
12
13; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
14; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
15; RUN:   FileCheck --check-prefix=ASM64 %s
16
17define dso_local void @vec_regs() {
18  entry:
19    call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
20      ret void
21}
22
23; MIR32-LABEL:   name:            vec_regs
24
25; MIR32:         fixedStack:      []
26; MIR32-NOT:     STXVD2X killed $v20
27; MIR32-NOT:     STXVD2X killed $v26
28; MIR32-NOT:     STXVD2X killed $v31
29; MIR32-LABEL:   INLINEASM
30; MIR32-NOT:     $v20 = LXVD2X
31; MIR32-NOT:     $v26 = LXVD2X
32; MIR32-NOT:     $v31 = LXVD2X
33; MIR32:         BLR implicit $lr, implicit $rm
34
35; MIR64-LABEL:   name:            vec_regs
36
37; MIR64:         fixedStack:      []
38; MIR64-NOT:     STXVD2X killed $v20
39; MIR64-NOT:     STXVD2X killed $v26
40; MIR64-NOT:     STXVD2X killed $v31
41; MIR64-LABEL:   INLINEASM
42; MIR64-NOT:     $v20 = LXVD2X
43; MIR64-NOT:     $v26 = LXVD2X
44; MIR64-NOT:     $v31 = LXVD2X
45; MIR64:         BLR8 implicit $lr8, implicit $rm
46
47; ASM32-LABEL:   .vec_regs:
48
49; ASM32-NOT:     20
50; ASM32-NOT:     26
51; ASM32-NOT:     31
52; ASM32-DAG:     #APP
53; ASM32-DAG:     #NO_APP
54; ASM32:         blr
55
56; ASM64-LABEL:   .vec_regs:
57
58; ASM64-NOT:     20
59; ASM64-NOT:     26
60; ASM64-NOT:     31
61; ASM64-DAG:     #APP
62; ASM64-DAG:     #NO_APP
63; ASM64:         blr
64
65define dso_local void @fprs_gprs_vecregs() {
66    call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
67      ret void
68}
69
70; MIR32-LABEL:   name:            fprs_gprs_vecregs
71
72; MIR32:         fixedStack:
73
74; MIR32:         liveins: $r14, $r25, $r31, $f14, $f21, $f31
75
76; MIR32-NOT:     STXVD2X killed $v20
77; MIR32-NOT:     STXVD2X killed $v26
78; MIR32-NOT:     STXVD2X killed $v31
79; MIR32-DAG:     STW killed $r14, -216, $r1 :: (store (s32) into %fixed-stack.5, align 8)
80; MIR32-DAG:     STW killed $r25, -172, $r1 :: (store (s32) into %fixed-stack.4)
81; MIR32-DAG:     STW killed $r31, -148, $r1 :: (store (s32) into %fixed-stack.3)
82; MIR32-DAG:     STFD killed $f14, -144, $r1 :: (store (s64) into %fixed-stack.2, align 16)
83; MIR32-DAG:     STFD killed $f21, -88, $r1 :: (store (s64) into %fixed-stack.1)
84; MIR32-DAG:     STFD killed $f31, -8, $r1 :: (store (s64) into %fixed-stack.0)
85
86; MIR32-LABEL:   INLINEASM
87
88; MIR32-NOT:     $v20 = LXVD2X
89; MIR32-NOT:     $v26 = LXVD2X
90; MIR32-NOT:     $v31 = LXVD2X
91; MIR32-DAG:     $r14 = LWZ -216, $r1 :: (load (s32) from %fixed-stack.5, align 8)
92; MIR32-DAG:     $r25 = LWZ -172, $r1 :: (load (s32) from %fixed-stack.4)
93; MIR32-DAG:     $r31 = LWZ -148, $r1 :: (load (s32) from %fixed-stack.3)
94; MIR32-DAG:     $f14 = LFD -144, $r1 :: (load (s64) from %fixed-stack.2, align 16)
95; MIR32-DAG:     $f21 = LFD -88, $r1 :: (load (s64) from %fixed-stack.1)
96; MIR32-DAG:     $f31 = LFD -8, $r1 :: (load (s64) from %fixed-stack.0)
97; MIR32-DAG:     BLR implicit $lr, implicit $rm
98
99; MIR64-LABEL:   name:            fprs_gprs_vecregs
100
101; MIR64:         fixedStack:
102
103; MIR64:         liveins: $x14, $x25, $x31, $f14, $f21, $f31
104
105; MIR64-NOT:     STXVD2X killed $v20
106; MIR64-NOT:     STXVD2X killed $v26
107; MIR64-NOT:     STXVD2X killed $v31
108; MIR64-DAG:     STD killed $x14, -288, $x1 :: (store (s64) into %fixed-stack.5, align 16)
109; MIR64-DAG:     STD killed $x25, -200, $x1 :: (store (s64) into %fixed-stack.4)
110; MIR64-DAG:     STD killed $x31, -152, $x1 :: (store (s64) into %fixed-stack.3)
111; MIR64-DAG:     STFD killed $f14, -144, $x1 :: (store (s64) into %fixed-stack.2, align 16)
112; MIR64-DAG:     STFD killed $f21, -88, $x1 :: (store (s64) into %fixed-stack.1)
113; MIR64-DAG:     STFD killed $f31, -8, $x1 :: (store (s64) into %fixed-stack.0)
114
115; MIR64-LABEL:   INLINEASM
116
117; MIR64-NOT:     $v20 = LXVD2X
118; MIR64-NOT:     $v26 = LXVD2X
119; MIR64-NOT:     $v31 = LXVD2X
120; MIR64-DAG:     $x14 = LD -288, $x1 :: (load (s64) from %fixed-stack.5, align 16)
121; MIR64-DAG:     $x25 = LD -200, $x1 :: (load (s64) from %fixed-stack.4)
122; MIR64-DAG:     $x31 = LD -152, $x1 :: (load (s64) from %fixed-stack.3)
123; MIR64-DAG:     $f14 = LFD -144, $x1 :: (load (s64) from %fixed-stack.2, align 16)
124; MIR64-DAG:     $f21 = LFD -88, $x1 :: (load (s64) from %fixed-stack.1)
125; MIR64-DAG:     $f31 = LFD -8, $x1 :: (load (s64) from %fixed-stack.0)
126; MIR64:         BLR8 implicit $lr8, implicit $rm
127
128;; We don't have -ppc-full-reg-names on AIX so can't reliably check-not for
129;; only vector registers numbers in this case.
130
131; ASM32-LABEL:   .fprs_gprs_vecregs:
132
133; ASM32-DAG:     stw 14, -216(1)                         # 4-byte Folded Spill
134; ASM32-DAG:     stw 25, -172(1)                         # 4-byte Folded Spill
135; ASM32-DAG:     stw 31, -148(1)                         # 4-byte Folded Spill
136; ASM32-DAG:     stfd 14, -144(1)                        # 8-byte Folded Spill
137; ASM32-DAG:     stfd 21, -88(1)                         # 8-byte Folded Spill
138; ASM32-DAG:     stfd 31, -8(1)                          # 8-byte Folded Spill
139; ASM32-DAG:     #APP
140; ASM32-DAG:     #NO_APP
141; ASM32-DAG:     lfd 31, -8(1)                           # 8-byte Folded Reload
142; ASM32-DAG:     lfd 21, -88(1)                          # 8-byte Folded Reload
143; ASM32-DAG:     lfd 14, -144(1)                         # 8-byte Folded Reload
144; ASM32-DAG:     lwz 31, -148(1)                         # 4-byte Folded Reload
145; ASM32-DAG:     lwz 25, -172(1)                         # 4-byte Folded Reload
146; ASM32-DAG:     lwz 14, -216(1)                         # 4-byte Folded Reload
147; ASM32:         blr
148
149; ASM64-LABEL:    .fprs_gprs_vecregs:
150
151; ASM64-DAG:     std 14, -288(1)                         # 8-byte Folded Spill
152; ASM64-DAG:     std 25, -200(1)                         # 8-byte Folded Spill
153; ASM64-DAG:     std 31, -152(1)                         # 8-byte Folded Spill
154; ASM64-DAG:     stfd 14, -144(1)                        # 8-byte Folded Spill
155; ASM64-DAG:     stfd 21, -88(1)                         # 8-byte Folded Spill
156; ASM64-DAG:     stfd 31, -8(1)                          # 8-byte Folded Spill
157; ASM64-DAG:     #APP
158; ASM64-DAG:     #NO_APP
159; ASM64-DAG:     lfd 31, -8(1)                           # 8-byte Folded Reload
160; ASM64-DAG:     lfd 21, -88(1)                          # 8-byte Folded Reload
161; ASM64-DAG:     lfd 14, -144(1)                         # 8-byte Folded Reload
162; ASM64-DAG:     ld 31, -152(1)                          # 8-byte Folded Reload
163; ASM64-DAG:     ld 25, -200(1)                          # 8-byte Folded Reload
164; ASM64-DAG:     ld 14, -288(1)                          # 8-byte Folded Reload
165; ASM64:         blr
166
167define dso_local void @all_fprs_and_vecregs() {
168    call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6}~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}"()
169      ret void
170}
171
172;; Check that reserved vectors are not used.
173; MIR32-LABEL:   all_fprs_and_vecregs
174
175; MIR32-NOT:     $v20
176; MIR32-NOT:     $v21
177; MIR32-NOT:     $v22
178; MIR32-NOT:     $v23
179; MIR32-NOT:     $v24
180; MIR32-NOT:     $v25
181; MIR32-NOT:     $v26
182; MIR32-NOT:     $v27
183; MIR32-NOT:     $v28
184; MIR32-NOT:     $v29
185; MIR32-NOT:     $v30
186; MIR32-NOT:     $v31
187
188; MIR64-LABEL:   all_fprs_and_vecregs
189
190; MIR64-NOT:     $v20
191; MIR64-NOT:     $v21
192; MIR64-NOT:     $v22
193; MIR64-NOT:     $v23
194; MIR64-NOT:     $v24
195; MIR64-NOT:     $v25
196; MIR64-NOT:     $v26
197; MIR64-NOT:     $v27
198; MIR64-NOT:     $v28
199; MIR64-NOT:     $v29
200; MIR64-NOT:     $v30
201; MIR64-NOT:     $v31
202