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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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| #
9a572164 |
| 30-Jun-2022 |
Fangrui Song <[email protected]> |
[ELF] Move InputFiles global variables (memoryBuffers, objectFiles, etc) into Ctx. NFC
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2 |
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| #
767e64fc |
| 25-Feb-2022 |
Fangrui Song <[email protected]> |
[ELF] Support some absolute/PC-relative relocation types for REL format
ctfconvert seems to use REL-format `.rel.SUNW_dof` for 32-bit architectures. ``` Binary file usr/ports/lang/perl5.32/work/perl
[ELF] Support some absolute/PC-relative relocation types for REL format
ctfconvert seems to use REL-format `.rel.SUNW_dof` for 32-bit architectures. ``` Binary file usr/ports/lang/perl5.32/work/perl-5.32.1/dtrace_mini.o matches [alfredo.junior@dell-a ~/tmp/llvm-bug]$ readelf -r dtrace_mini.o
Relocation section (.rel.SUNW_dof): r_offset r_info r_type st_value st_name 00000184 0000281a R_PPC_REL32 00000000 $dtrace1772974259.Perl_dtrace_probe_load ```
Support R_PPC_REL32 to fix `ld.lld: error: drti.c:(.SUNW_dof+0x4E4): internal linker error: cannot read addend for relocation R_PPC_REL32`. While here, add some common relocation types for AArch64, PPC, and PPC64. We perform minimum tests.
Reviewed By: adalava, arichardson
Differential Revision: https://reviews.llvm.org/D120535
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| #
38fbedab |
| 24-Feb-2022 |
Fangrui Song <[email protected]> |
[ELF] Don't rely on Symbols.h's transitive inclusion of InputFiles.h. NFC
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| #
53b59fdc |
| 15-Feb-2022 |
Fangrui Song <[email protected]> |
[ELF][PPC64] Fix assertion failure for branches to hidden undefined weak for -no-pie
Reported by Stefan Pintilie in D119773.
For a branch to a hidden undefined weak symbol, there is an `assert(sym-
[ELF][PPC64] Fix assertion failure for branches to hidden undefined weak for -no-pie
Reported by Stefan Pintilie in D119773.
For a branch to a hidden undefined weak symbol, there is an `assert(sym->getVA());` failure in PPC64LongBranchTargetSection::writeTo for a -no-pie link. The root cause is that we unnecessarily create the thunk for the -no-pie link.
Fix this by changing the condition to just `s.isUndefined()`. See the inline comment.
Rename ppc64-weak-undef-call.s to ppc64-undefined-weak.s to be consistent with other architectures.
Reviewed By: sfertile, stefanp
Differential Revision: https://reviews.llvm.org/D119787
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Revision tags: llvmorg-14.0.0-rc1 |
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| #
977a1a52 |
| 06-Feb-2022 |
Fangrui Song <[email protected]> |
[ELF] Symbol::replace: use the old nameData/nameSize. NFC
Currently `this->getName() == newSym.getName()`. By keeping the old nameData/nameSize, newSym's nameData/nameSize will be ignored. The call
[ELF] Symbol::replace: use the old nameData/nameSize. NFC
Currently `this->getName() == newSym.getName()`. By keeping the old nameData/nameSize, newSym's nameData/nameSize will be ignored. The call sites can avoid calling getName().
printTraceSymbol needs to take the symbol name since `other`'s name is empty.
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| #
53fc5d9b |
| 04-Feb-2022 |
Fangrui Song <[email protected]> |
[ELF] Support R_PPC_NONE/R_PPC64_NONE in getImplicitAddend
Similar to f457863ae345d2635026501f5383e0e625869639
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Revision tags: llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3 |
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| #
83d59e05 |
| 20-Jan-2022 |
Alexandre Ganea <[email protected]> |
Re-land [LLD] Remove global state in lldCommon
Move all variables at file-scope or function-static-scope into a hosting structure (lld::CommonLinkerContext) that lives at lldMain()-scope. Drivers wi
Re-land [LLD] Remove global state in lldCommon
Move all variables at file-scope or function-static-scope into a hosting structure (lld::CommonLinkerContext) that lives at lldMain()-scope. Drivers will inherit from this structure and add their own global state, in the same way as for the existing COFFLinkerContext.
See discussion in https://lists.llvm.org/pipermail/llvm-dev/2021-June/151184.html
The previous land f860fe362282ed69b9d4503a20e5d20b9a041189 caused issues in https://lab.llvm.org/buildbot/#/builders/123/builds/8383, fixed by 22ee510dac9440a74b2e5b3fe3ff13ccdbf55af3.
Differential Revision: https://reviews.llvm.org/D108850
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e6b15394 |
| 16-Jan-2022 |
Alexandre Ganea <[email protected]> |
Revert [LLD] Remove global state in lldCommon
It seems to be causing issues on https://lab.llvm.org/buildbot/#/builders/123/builds/8383
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f860fe36 |
| 16-Jan-2022 |
Alexandre Ganea <[email protected]> |
[LLD] Remove global state in lldCommon
Move all variables at file-scope or function-static-scope into a hosting structure (lld::CommonLinkerContext) that lives at lldMain()-scope. Drivers will inher
[LLD] Remove global state in lldCommon
Move all variables at file-scope or function-static-scope into a hosting structure (lld::CommonLinkerContext) that lives at lldMain()-scope. Drivers will inherit from this structure and add their own global state, in the same way as for the existing COFFLinkerContext.
See discussion in https://lists.llvm.org/pipermail/llvm-dev/2021-June/151184.html
Differential Revision: https://reviews.llvm.org/D108850
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Revision tags: llvmorg-13.0.1-rc2 |
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| #
5d3bd7f3 |
| 09-Jan-2022 |
Fangrui Song <[email protected]> |
[ELF] Move gotIndex/pltIndex/globalDynIndex to SymbolAux
to decrease sizeof(SymbolUnion) by 8 on ELF64 platforms.
Symbols needing such information are typically 1% or fewer (5134 out of 560520 when
[ELF] Move gotIndex/pltIndex/globalDynIndex to SymbolAux
to decrease sizeof(SymbolUnion) by 8 on ELF64 platforms.
Symbols needing such information are typically 1% or fewer (5134 out of 560520 when linking clang, 19898 out of 5550705 when linking chrome). Storing them elsewhere can decrease memory usage and symbol initialization time. There is a ~0.8% saving on max RSS when linking a large program.
Future direction:
* Move some of dynsymIndex/verdefIndex/versionId to SymbolAux * Support mixed TLSDESC and TLS GD without increasing sizeof(SymbolUnion)
Reviewed By: peter.smith
Differential Revision: https://reviews.llvm.org/D116281
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Revision tags: llvmorg-13.0.1-rc1 |
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d71bb6a4 |
| 10-Nov-2021 |
Fangrui Song <[email protected]> |
[ELF] Inline isPPC64SmallCodeModelTocReloc which is only called once. NFC
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| #
ecc93ed2 |
| 27-Oct-2021 |
Fangrui Song <[email protected]> |
[ELF] Replace InputBaseSection::{areRelocsRela,firstRelocation,numRelocation} with relSecIdx
For `InputSection` `.foo`, its `InputBaseSection::{areRelocsRela,firstRelocation,numRelocation}` basicall
[ELF] Replace InputBaseSection::{areRelocsRela,firstRelocation,numRelocation} with relSecIdx
For `InputSection` `.foo`, its `InputBaseSection::{areRelocsRela,firstRelocation,numRelocation}` basically encode the information of `.rel[a].foo`. However, one uint32_t (the relocation section index) suffices. See the implementation of `relsOrRelas`.
This change decreases sizeof(InputSection) from 184 to 176 on 64-bit Linux.
The maximum resident set size linking a large application (1.2G output) decreases by 0.39%.
Differential Revision: https://reviews.llvm.org/D112513
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d23fd8ae |
| 25-Sep-2021 |
Fangrui Song <[email protected]> |
[ELF] Replace noneRel = R_*_NONE with static constexpr. NFC
All architectures define R_*_NONE to 0.
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| #
40cd4db4 |
| 25-Sep-2021 |
Fangrui Song <[email protected]> |
[ELF] Default gotBaseSymInGotPlt to false (NFC for most architectures)
Most architectures use .got instead of .got.plt, so switching the default can minimize customization.
This fixes an issue for
[ELF] Default gotBaseSymInGotPlt to false (NFC for most architectures)
Most architectures use .got instead of .got.plt, so switching the default can minimize customization.
This fixes an issue for SPARC V9 which uses .got . AVR, AMDGPU, and MSP430 don't seem to use _GLOBAL_OFFSET_TABLE_.
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Revision tags: llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4 |
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| #
f21704e0 |
| 22-Mar-2021 |
Stefan Pintilie <[email protected]> |
[LLD][PowerPC] Fix bug in PC-Relative initial exec
There is a bug when initial exec is relaxed to local exec. In the following situation:
InitExec.c ``` extern __thread unsigned TGlobal; unsigned g
[LLD][PowerPC] Fix bug in PC-Relative initial exec
There is a bug when initial exec is relaxed to local exec. In the following situation:
InitExec.c ``` extern __thread unsigned TGlobal; unsigned getConst(unsigned*); unsigned addVal(unsigned, unsigned*);
unsigned GetAddrT() { return addVal(getConst(&TGlobal), &TGlobal); } ```
Def.c ``` __thread unsigned TGlobal;
unsigned getConst(unsigned* A) { return *A + 3; }
unsigned addVal(unsigned A, unsigned* B) { return A + *B; } ```
The problem is in InitExec.c but Def.c is required if you want to link the example and see the problem. To compile everything: ``` clang -O3 -mcpu=pwr10 -c InitExec.c clang -O3 -mcpu=pwr10 -c Def.c ld.lld InitExec.o Def.o -o IeToLe ```
If you objdump the problem object file: ``` $ llvm-objdump -dr --mcpu=pwr10 InitExec.o ``` you will get the following assembly: ``` 0000000000000000 <GetAddrT>: 0: a6 02 08 7c mflr 0 4: f0 ff c1 fb std 30, -16(1) 8: 10 00 01 f8 std 0, 16(1) c: d1 ff 21 f8 stdu 1, -48(1) 10: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1 0000000000000010: R_PPC64_GOT_TPREL_PCREL34 TGlobal 18: 14 6a c3 7f add 30, 3, 13 0000000000000019: R_PPC64_TLS TGlobal 1c: 78 f3 c3 7f mr 3, 30 20: 01 00 00 48 bl 0x20 0000000000000020: R_PPC64_REL24_NOTOC getConst 24: 78 f3 c4 7f mr 4, 30 28: 30 00 21 38 addi 1, 1, 48 2c: 10 00 01 e8 ld 0, 16(1) 30: f0 ff c1 eb ld 30, -16(1) 34: a6 03 08 7c mtlr 0 38: 00 00 00 48 b 0x38 0000000000000038: R_PPC64_REL24_NOTOC addVal ``` The lines of interest are: ``` 10: 00 00 10 04 00 00 60 e4 pld 3, 0(0), 1 0000000000000010: R_PPC64_GOT_TPREL_PCREL34 TGlobal 18: 14 6a c3 7f add 30, 3, 13 0000000000000019: R_PPC64_TLS TGlobal 1c: 78 f3 c3 7f mr 3, 30 ``` Which once linked gets turned into: ``` 10010210: ff ff 03 06 00 90 6d 38 paddi 3, 13, -28672, 0 10010218: 00 00 00 60 nop 1001021c: 78 f3 c3 7f mr 3, 30 ``` The problem is that register 30 is never set after the optimization.
Therefore it is not correct to relax the above instructions by replacing the add instruction with a nop. Instead the add instruction should be replaced with a copy (mr) instruction. If the add uses the same resgiter as input and as ouput then it is safe to continue to replace the add with a nop.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D95262
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Revision tags: llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2 |
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| #
5fcb412e |
| 19-Jan-2021 |
Fangrui Song <[email protected]> |
[ELF] Support R_PPC64_ADDR16_HIGH
R_PPC64_ADDR16_HI represents bits 16-31 of a 32-bit value R_PPC64_ADDR16_HIGH represents bits 16-31 of a 64-bit value.
In the Linux kernel, `LOAD_REG_IMMEDIATE_SYM
[ELF] Support R_PPC64_ADDR16_HIGH
R_PPC64_ADDR16_HI represents bits 16-31 of a 32-bit value R_PPC64_ADDR16_HIGH represents bits 16-31 of a 64-bit value.
In the Linux kernel, `LOAD_REG_IMMEDIATE_SYM` defined in `arch/powerpc/include/asm/ppc_asm.h` uses @l, @high, @higher, @highest to load the 64-bit value of a symbol.
Fixes https://github.com/ClangBuiltLinux/linux/issues/1260
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e12e0d66 |
| 19-Jan-2021 |
Fangrui Song <[email protected]> |
[ELF] Error for out-of-range R_PPC64_ADDR16_HA, R_PPC64_ADDR16_HI and their friends
There are no tests for REL16_* and TPREL16_*.
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Revision tags: llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2 |
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22c1bd57 |
| 18-Dec-2020 |
Fangrui Song <[email protected]> |
[ELF] Rename R_TLS to R_TPREL and R_NEG_TLS to R_TPREL_NEG. NFC
The scope of R_TLS (TP offset relocation types (TPREL/TPOFF) used for the local-exec TLS model) is actually narrower than its name may
[ELF] Rename R_TLS to R_TPREL and R_NEG_TLS to R_TPREL_NEG. NFC
The scope of R_TLS (TP offset relocation types (TPREL/TPOFF) used for the local-exec TLS model) is actually narrower than its name may imply. R_TLS_NEG is only used by Solaris R_386_TLS_LE_32.
Rename them so that they will be less confusing.
Reviewed By: grimar, psmith, rprichard
Differential Revision: https://reviews.llvm.org/D93467
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Revision tags: llvmorg-11.0.1-rc1 |
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50564ca0 |
| 25-Nov-2020 |
Fangrui Song <[email protected]> |
[ELF] Rename adjustRelaxExpr to adjustTlsExpr and delete the unused `data` parameter. NFC
Reviewed By: psmith
Differential Revision: https://reviews.llvm.org/D91995
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572d1839 |
| 25-Nov-2020 |
Fangrui Song <[email protected]> |
[ELF] Add TargetInfo::adjustGotPcExpr for `R_GOT_PC` relaxations. NFC
With this change, `TargetInfo::adjustRelaxExpr` is only related to TLS relaxations and a subsequent clean-up can delete the `dat
[ELF] Add TargetInfo::adjustGotPcExpr for `R_GOT_PC` relaxations. NFC
With this change, `TargetInfo::adjustRelaxExpr` is only related to TLS relaxations and a subsequent clean-up can delete the `data` parameter.
Differential Revision: https://reviews.llvm.org/D92079
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c6561ccf |
| 23-Oct-2020 |
Stefan Pintilie <[email protected]> |
[PowerPC][LLD] Support for PC Relative TLS for Local Dynamic
Add support to LLD for PC Relative Thread Local Storage for Local Dynamic. This patch adds support for two relocations: R_PPC64_GOT_TLSLD
[PowerPC][LLD] Support for PC Relative TLS for Local Dynamic
Add support to LLD for PC Relative Thread Local Storage for Local Dynamic. This patch adds support for two relocations: R_PPC64_GOT_TLSLD_PCREL34 and R_PPC64_DTPREL34.
The Local Dynamic code is: ``` pla r3, x@got@tlsld@pcrel R_PPC64_GOT_TLSLD_PCREL34 bl __tls_get_addr@notoc(x@tlsld) R_PPC64_TLSLD R_PPC64_REL24_NOTOC ... paddi r9, r3, x@dtprel R_PPC64_DTPREL34 ```
After relaxation to Local Exec: ``` paddi r3, r13, 0x1000 nop ... paddi r9, r3, x@dtprel R_PPC64_DTPREL34 ```
Reviewed By: NeHuang, sfertile
Differential Revision: https://reviews.llvm.org/D87504
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Revision tags: llvmorg-11.0.0, llvmorg-11.0.0-rc6 |
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| #
88f2fe5c |
| 01-Oct-2020 |
Fangrui Song <[email protected]> |
Raland D87318 [LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in Genera
Raland D87318 [LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.
The compiler will produce code that looks like: ``` pla r3, x@got@tlsgd@pcrel R_PPC64_GOT_TLSGD_PCREL34 bl __tls_get_addr@notoc(x@tlsgd) R_PPC64_TLSGD R_PPC64_REL24_NOTOC ``` LLD should be able to correctly compute the relocation for R_PPC64_GOT_TLSGD_PCREL34 as well as do the following two relaxations where possible: General Dynamic to Local Exec: ``` paddi r3, r13, x@tprel nop ``` and General Dynamic to Initial Exec: ``` pld r3, x@got@tprel@pcrel add r3, r3, r13 ``` Note: This patch adds support for the PC Relative (no TOC) version of General Dynamic on top of the existing support for the TOC version of General Dynamic. The ABI does not provide any way to tell by looking only at the relocation `R_PPC64_TLSGD` when it is being used in a TOC instruction sequence or and when it is being used in a no TOC sequence. The TOC sequence should always be 4 byte aligned. This patch adds one to the offset of the relocation when it is being used in a no TOC sequence. In this way LLD can tell by looking at the alignment of the offset of `R_PPC64_TLSGD` whether or not it is being used as part of a TOC or no TOC sequence.
Reviewed By: NeHuang, sfertile, MaskRay
Differential Revision: https://reviews.llvm.org/D87318
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| #
5f3e565f |
| 01-Oct-2020 |
Stefan Pintilie <[email protected]> |
Revert "[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic"
This reverts commit 79122868f9a3909cfd94d51e9bfe960917a1be05.
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79122868 |
| 01-Oct-2020 |
Stefan Pintilie <[email protected]> |
[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.
Th
[LLD][PowerPC] Add support for R_PPC64_GOT_TLSGD_PCREL34 used in TLS General Dynamic
Add Thread Local Storage support for the 34 bit relocation R_PPC64_GOT_TLSGD_PCREL34 used in General Dynamic.
The compiler will produce code that looks like: ``` pla r3, x@got@tlsgd@pcrel R_PPC64_GOT_TLSGD_PCREL34 bl __tls_get_addr@notoc(x@tlsgd) R_PPC64_TLSGD R_PPC64_REL24_NOTOC ``` LLD should be able to correctly compute the relocation for R_PPC64_GOT_TLSGD_PCREL34 as well as do the following two relaxations where possible: General Dynamic to Local Exec: ``` paddi r3, r13, x@tprel nop ``` and General Dynamic to Initial Exec: ``` pld r3, x@got@tprel@pcrel add r3, r3, r13 ``` Note: This patch adds support for the PC Relative (no TOC) version of General Dynamic on top of the existing support for the TOC version of General Dynamic. The ABI does not provide any way to tell by looking only at the relocation `R_PPC64_TLSGD` when it is being used in a TOC instruction sequence or and when it is being used in a no TOC sequence. The TOC sequence should always be 4 byte aligned. This patch adds one to the offset of the relocation when it is being used in a no TOC sequence. In this way LLD can tell by looking at the alignment of the offset of `R_PPC64_TLSGD` whether or not it is being used as part of a TOC or no TOC sequence.
Reviewed By: NeHuang, sfertile, MaskRay
Differential Revision: https://reviews.llvm.org/D87318
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Revision tags: llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4 |
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| #
8c53282d |
| 25-Sep-2020 |
Stefan Pintilie <[email protected]> |
[PowerPC][NFC] Merged two switch entries.
Two switch entries did exactly the same thing. This patch merges them.
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