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Searched refs:IndexReg (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp518 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
520 if (AluDestReg == IndexReg) { in optLEAALU()
521 if (BaseReg == IndexReg) in optLEAALU()
523 std::swap(BaseReg, IndexReg); in optLEAALU()
526 if (BaseReg == IndexReg) in optLEAALU()
584 if (IndexReg != 0) in optTwoAddrLEA()
585 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
597 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
772 if (IndexReg != 0) in processInstrForSlow3OpLEA()
773 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
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H A DX86InstrBuilder.h54 unsigned IndexReg; member
60 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
108 AM.IndexReg = Op2.getReg(); in getAddressFromInstr()
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
H A DX86InsertPrefetch.cpp84 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
88 (IndexReg == 0 || in IsMemOpCompatibleWithPrefetch()
89 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) || in IsMemOpCompatibleWithPrefetch()
90 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)); in IsMemOpCompatibleWithPrefetch()
H A DX86AsmPrinter.cpp290 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
300 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
321 assert(IndexReg.getReg() != X86::ESP && in PrintLeaMemReference()
328 if (IndexReg.getReg()) { in PrintLeaMemReference()
387 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
417 if (IndexReg.getReg()) { in PrintIntelMemReference()
430 if (DispVal || (!IndexReg.getReg() && !HasBaseReg)) { in PrintIntelMemReference()
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
813 if (AM.IndexReg == 0) { in handleConstantAddresses()
816 return AM.IndexReg != 0; in handleConstantAddresses()
900 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
932 if (IndexReg == 0 && in X86SelectAddress()
938 if (IndexReg == 0) in X86SelectAddress()
951 AM.IndexReg = IndexReg; in X86SelectAddress()
1108 if (AM.IndexReg == 0) { in X86SelectCallAddress()
1111 return AM.IndexReg != 0; in X86SelectCallAddress()
3964 if (IndexReg == MO.getReg()) in tryToFoldLoadIntoMI()
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H A DX86ISelDAGToDAG.cpp69 SDValue IndexReg; member
122 if (IndexReg.getNode()) in dump()
283 AM.IndexReg = Neg; in getAddressOperands()
1941 AM.IndexReg = And; in foldMaskAndShiftToExtract()
2010 AM.IndexReg = NewAnd; in foldMaskedShiftToScaledMask()
2121 AM.IndexReg = NewSRL; in foldMaskAndShiftToScale()
2180 AM.IndexReg = NewAnd; in foldMaskedShiftToBEXTR()
2408 AM.IndexReg = RHS; in matchAddressRecursively()
2509 AM.IndexReg = Zext; in matchAddressRecursively()
2529 AM.IndexReg = N; in matchAddressBase()
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H A DX86SpeculativeLoadHardening.cpp1343 unsigned BaseReg = 0, IndexReg = 0; in tracePredStateThroughBlocksAndHarden() local
1348 IndexReg = IndexMO.getReg(); in tracePredStateThroughBlocksAndHarden()
1350 if (!BaseReg && !IndexReg) in tracePredStateThroughBlocksAndHarden()
1359 (IndexReg && LoadDepRegs.test(IndexReg))) in tracePredStateThroughBlocksAndHarden()
1372 !HardenedAddrRegs.count(IndexReg)) { in tracePredStateThroughBlocksAndHarden()
1383 if (IndexReg) in tracePredStateThroughBlocksAndHarden()
1384 HardenedAddrRegs.insert(IndexReg); in tracePredStateThroughBlocksAndHarden()
H A DX86MCInstLower.cpp1125 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in emitNop() local
1126 IndexReg = Displacement = SegmentReg = 0; in emitNop()
1154 IndexReg = X86::RAX; in emitNop()
1160 IndexReg = X86::RAX; in emitNop()
1171 IndexReg = X86::RAX; in emitNop()
1177 IndexReg = X86::RAX; in emitNop()
1183 IndexReg = X86::RAX; in emitNop()
1207 .addReg(IndexReg) in emitNop()
/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp678 if (IndexReg) in onPlus()
737 if (IndexReg) in onMinus()
796 if (IndexReg) in onRegister()
878 if (IndexReg) in onInteger()
1307 if (IndexReg != 0 && in CheckBaseRegAndIndexRegAndScale()
1308 !(IndexReg == X86::EIZ || IndexReg == X86::RIZ || in CheckBaseRegAndIndexRegAndScale()
1320 IndexReg == X86::EIP || IndexReg == X86::RIP || in CheckBaseRegAndIndexRegAndScale()
1321 IndexReg == X86::ESP || IndexReg == X86::RSP) { in CheckBaseRegAndIndexRegAndScale()
1363 (IndexReg != X86::SI && IndexReg != X86::DI)) { in CheckBaseRegAndIndexRegAndScale()
2595 (IndexReg == X86::ESP || IndexReg == X86::RSP)) in parseIntelOperand()
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H A DX86Operand.h67 unsigned IndexReg; member
147 if (Mem.IndexReg) in print()
149 << X86IntelInstPrinter::getRegisterName(Mem.IndexReg); in print()
203 return Mem.IndexReg; in getMemIndexReg()
340 return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR; in isMemIndexReg()
691 Res->Mem.IndexReg = 0;
707 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
715 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
726 Res->Mem.IndexReg = IndexReg;
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp69 SDValue IndexReg; member
103 return BaseType == Base::RegBase && IndexReg.getNode() != nullptr; in hasIndexReg()
147 void setIndexReg(SDValue Reg) { IndexReg = Reg; } in setIndexReg()
160 if (IndexReg.getNode()) { in dump()
161 IndexReg.getNode()->dump(); in dump()
402 AM.IndexReg = N; in matchAddressBase()
538 AM.IndexReg = N.getOperand(1); in matchADD()
766 if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) { in SelectARII()
767 Base = AM.IndexReg; in SelectARII()
771 Index = AM.IndexReg; in SelectARII()
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/llvm-project-15.0.7/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h68 StringRef IndexReg; member
73 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
84 bool hasIndexReg() const { return !IndexReg.empty(); } in hasIndexReg()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp274 for (const unsigned IndexReg : PossibleIndexRegs.set_bits()) { in generateLEATemplatesCommon() local
282 setMemOp(IT, 3, MCOperand::createReg(IndexReg)); in generateLEATemplatesCommon()
289 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow); in generateLEATemplatesCommon()
300 RegInfo.getName(IndexReg), Scale, Disp) in generateLEATemplatesCommon()
337 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
397 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
403 State.getRATC().getRegister(IndexReg).aliasedBits()); in generateCodeTemplates()
/llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp185 unsigned IndexReg; member
367 return Mem.IndexReg; in getMemIndexReg()
698 Op->Mem.IndexReg = 0; in MorphToMEMri()
709 Op->Mem.IndexReg = 0; in MorphToMEMzi()
720 Op->Mem.IndexReg = Index; in MorphToMEMrri()
732 Op->Mem.IndexReg = 0; in MorphToMEMrii()
743 Op->Mem.IndexReg = Index; in MorphToMEMzri()
754 Op->Mem.IndexReg = 0; in MorphToMEMzii()
1249 unsigned IndexReg = 0; in parseMEMOperand() local
1253 if (ParseRegister(IndexReg, S, E)) in parseMEMOperand()
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/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp330 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
338 assert(IndexReg.getReg() == 0 && !ForceSIB && in emitMemModRMByte()
425 if (IndexReg.getReg()) { in emitMemModRMByte()
426 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; in emitMemModRMByte()
456 assert(IndexReg.getReg() == 0 && "Unexpected index register!"); in emitMemModRMByte()
478 !ForceSIB && IndexReg.getReg() == 0 && in emitMemModRMByte()
543 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
580 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(IndexReg) : 4; in emitMemModRMByte()
H A DX86ATTInstPrinter.cpp427 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
437 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
444 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
449 if (IndexReg.getReg()) { in printMemReference()
H A DX86IntelInstPrinter.cpp385 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
399 if (IndexReg.getReg()) { in printMemReference()
413 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
H A DX86MCTargetDesc.cpp650 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
653 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || in evaluateMemoryOperandAddress()
676 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in getMemoryOperandRelocationOffset() local
681 IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || !Disp.isImm()) in getMemoryOperandRelocationOffset()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp167 unsigned &IndexReg);
421 unsigned &IndexReg) { in PPCSimplifyAddress() argument
442 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
506 unsigned IndexReg = 0; in PPCEmitLoad() local
507 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitLoad()
579 if (IndexReg) in PPCEmitLoad()
580 MIB.addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
655 unsigned IndexReg = 0; in PPCEmitStore() local
656 PPCSimplifyAddress(Addr, UseOffset, IndexReg); in PPCEmitStore()
725 if (IndexReg) in PPCEmitStore()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DLoadStoreOpt.h38 Register IndexReg; member
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp87 Info.IndexReg = Register(); in getPointerInfo()
98 Info.IndexReg = PtrAddRHS; in getPointerInfo()
/llvm-project-15.0.7/bolt/lib/Target/X86/
H A DX86MCPlusBuilder.cpp2299 unsigned BaseReg, IndexReg, SegmentReg; in analyzeVirtualMethodCall() local
2309 if (Scale == 1 && IndexReg == X86::NoRegister && in analyzeVirtualMethodCall()
2336 evaluateX86MemoryOperand(CurInst, &BaseReg, &Scale, &IndexReg, in analyzeVirtualMethodCall()
2340 IndexReg == X86::NoRegister && SegmentReg == X86::NoRegister && in analyzeVirtualMethodCall()
2446 const MCPhysReg &IndexReg, int64_t Offset, in createLoad() argument
2462 Inst.addOperand(MCOperand::createReg(IndexReg)); in createLoad()
2497 const MCOperand &IndexReg, const MCOperand &Offset, in createIJmp32Frag() argument
2513 Load.addOperand(IndexReg); in createIJmp32Frag()
3652 uint16_t IndexReg = getAnnotationAs<uint16_t>(IJmpInst, "JTIndexReg"); in jumpTablePromotion() local
3653 if (IndexReg == 0) in jumpTablePromotion()
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/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp203 uint16_t IndexReg, AllocatorIdTy AllocId) { in setJumpTable() argument
207 getOrCreateAnnotationAs<uint16_t>(Inst, "JTIndexReg", AllocId) = IndexReg; in setJumpTable()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DIndirectCallPromotion.cpp384 unsigned BaseReg, IndexReg; in maybeGetHotJumpTableTargets() local
390 MemLocInstr, BaseReg, IndexReg, DispValue, DispExpr, PCRelBaseOut); in maybeGetHotJumpTableTargets()
409 << "IndexReg = " << BC.MRI->getName(IndexReg) << ", " in maybeGetHotJumpTableTargets()
516 BC.MIB->getOrCreateAnnotationAs<uint16_t>(CallInst, "JTIndexReg") = IndexReg; in maybeGetHotJumpTableTargets()
/llvm-project-15.0.7/bolt/include/bolt/Core/
H A DMCPlusBuilder.h1072 bool setJumpTable(MCInst &Inst, uint64_t Value, uint16_t IndexReg,
1505 const MCPhysReg &IndexReg, int64_t Offset, in createLoad() argument
1529 const MCOperand &Scale, const MCOperand &IndexReg, in createIJmp32Frag() argument

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