427     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anonad53f99c0111::X86AsmParser::IntelExprStateMachine
460     unsigned getIndexReg() const { return IndexReg; }  in getIndexReg()
678             if (IndexReg)  in onPlus()
680             IndexReg = TmpReg;  in onPlus()
737             if (IndexReg)  in onMinus()
739             IndexReg = TmpReg;  in onMinus()
796           if (IndexReg)  in onRegister()
799           IndexReg = Reg;  in onRegister()
878           if (IndexReg)  in onInteger()
880           IndexReg = TmpReg;  in onInteger()
981             if (IndexReg)  in onRBrac()
983             IndexReg = TmpReg;  in onRBrac()
1139                                unsigned BaseReg, unsigned IndexReg,
1291 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1307   if (IndexReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1308       !(IndexReg == X86::EIZ || IndexReg == X86::RIZ ||  in CheckBaseRegAndIndexRegAndScale()
1309         X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1310         X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1311         X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1312         X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1313         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1314         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg))) {  in CheckBaseRegAndIndexRegAndScale()
1319   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1320       IndexReg == X86::EIP || IndexReg == X86::RIP ||  in CheckBaseRegAndIndexRegAndScale()
1321       IndexReg == X86::ESP || IndexReg == X86::RSP) {  in CheckBaseRegAndIndexRegAndScale()
1336       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1341   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1343         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1344          X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1345          IndexReg == X86::EIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1350         (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1351          X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1352          IndexReg == X86::RIZ)) {  in CheckBaseRegAndIndexRegAndScale()
1357       if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||  in CheckBaseRegAndIndexRegAndScale()
1358           X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {  in CheckBaseRegAndIndexRegAndScale()
1363           (IndexReg != X86::SI && IndexReg != X86::DI)) {  in CheckBaseRegAndIndexRegAndScale()
1744     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1777   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForMSInlineAsm()
1780                                              BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1788       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2587   unsigned IndexReg = SM.getIndexReg();  in parseIntelOperand()  local
2588   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2595       (IndexReg == X86::ESP || IndexReg == X86::RSP))  in parseIntelOperand()
2596     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2601       !(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2602         X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||  in parseIntelOperand()
2603         X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&  in parseIntelOperand()
2607     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2610       X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))  in parseIntelOperand()
2621       (IndexReg == X86::BX || IndexReg == X86::BP))  in parseIntelOperand()
2622     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2624   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2625       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2629     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,  in parseIntelOperand()
2649       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2664   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2666         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
2967   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
3006         IndexReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
3011         if (IndexReg == X86::RIP)  in ParseMemOperand()
3044   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3051   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3055   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3057                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()