Lines Matching refs:IndexReg
463 Register IndexReg = LeaI->getOperand(1 + X86::AddrIndexReg).getReg(); in checkRegUsage() local
481 if (TRI->regsOverlap(Reg, IndexReg)) { in checkRegUsage()
515 Register IndexReg = I->getOperand(1 + X86::AddrIndexReg).getReg(); in optLEAALU() local
518 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optLEAALU()
520 if (AluDestReg == IndexReg) { in optLEAALU()
521 if (BaseReg == IndexReg) in optLEAALU()
523 std::swap(BaseReg, IndexReg); in optLEAALU()
526 if (BaseReg == IndexReg) in optLEAALU()
540 .addReg(IndexReg, KilledIndex ? RegState::Kill : 0); in optLEAALU()
574 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
584 if (IndexReg != 0) in optTwoAddrLEA()
585 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in optTwoAddrLEA()
593 if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 && in optTwoAddrLEA()
594 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
597 std::swap(BaseReg, IndexReg); in optTwoAddrLEA()
602 .addReg(BaseReg).addReg(IndexReg) in optTwoAddrLEA()
607 .addReg(BaseReg).addReg(IndexReg); in optTwoAddrLEA()
609 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
641 } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) { in optTwoAddrLEA()
767 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
772 if (IndexReg != 0) in processInstrForSlow3OpLEA()
773 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
778 bool IsInefficientIndex = isInefficientLEAReg(IndexReg); in processInstrForSlow3OpLEA()
794 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) { in processInstrForSlow3OpLEA()
797 std::swap(BaseReg, IndexReg); in processInstrForSlow3OpLEA()
803 .addReg(IndexReg) in processInstrForSlow3OpLEA()
809 .addReg(IndexReg); in processInstrForSlow3OpLEA()
863 bool BIK = Base.isKill() && BaseReg != IndexReg; in processInstrForSlow3OpLEA()