Lines Matching refs:IndexReg
217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
731 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
750 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
813 if (AM.IndexReg == 0) { in handleConstantAddresses()
815 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
816 return AM.IndexReg != 0; in handleConstantAddresses()
900 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
932 if (IndexReg == 0 && in X86SelectAddress()
937 IndexReg = getRegForGEPIndex(Op); in X86SelectAddress()
938 if (IndexReg == 0) in X86SelectAddress()
951 AM.IndexReg = IndexReg; in X86SelectAddress()
1054 (AM.Base.Reg != 0 || AM.IndexReg != 0)) in X86SelectCallAddress()
1071 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in X86SelectCallAddress()
1108 if (AM.IndexReg == 0) { in X86SelectCallAddress()
1110 AM.IndexReg = GetCallRegForValue(V); in X86SelectCallAddress()
1111 return AM.IndexReg != 0; in X86SelectCallAddress()
3801 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr) in X86MaterializeGV()
3959 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg) in tryToFoldLoadIntoMI()
3962 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI() local
3964 if (IndexReg == MO.getReg()) in tryToFoldLoadIntoMI()
3966 MO.setReg(IndexReg); in tryToFoldLoadIntoMI()