| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1273 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1552 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
2922 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
3455 EVT FinalVT = InVT; in SplitVecOp_TruncateHelper()
4544 if (InVT.isVector()) in WidenVecRes_BITCAST()
4564 InVT = NInVT; in WidenVecRes_BITCAST()
4580 if (WidenVT.bitsEq(InVT)) in WidenVecRes_BITCAST()
4595 if (InVT.isVector()) { in WidenVecRes_BITCAST()
4605 if (InVT.isVector()) { in WidenVecRes_BITCAST()
6661 if (InVT == NVT) in ModifyToType()
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| H A D | LegalizeTypesGeneric.cpp | 44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 379 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
385 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
1151 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1158 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1159 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1356 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
2270 EVT InVT = Op.getValueType(); in PromoteIntOp_VECREDUCE() local
2271 EVT EltVT = InVT.getVectorElementType(); in PromoteIntOp_VECREDUCE()
5186 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
5235 EVT InVT = InOp0.getValueType(); in PromoteIntRes_EXTRACT_SUBVECTOR() local
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| H A D | DAGCombiner.cpp | 20560 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
20579 InVT.getVectorNumElements()) { in reduceBuildVecToShuffle()
20766 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
20776 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
21804 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
21806 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
21810 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
22269 EVT InVT = Op0.getOperand(0).getValueType(); in combineShuffleOfBitcast() local
22270 if (!InVT.isVector() || in combineShuffleOfBitcast()
22279 int InLanes = InVT.getVectorNumElements(); in combineShuffleOfBitcast()
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| H A D | SelectionDAG.cpp | 3462 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3463 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3474 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3475 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3490 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3491 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
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| H A D | LegalizeDAG.cpp | 2143 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2144 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), in ExpandArgFPLibCall()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2675 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2677 InVT = MVT::i32; in truncateVectorWithNARROW()
2681 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithNARROW()
2690 Lo = DAG.getBitcast(InVT, Lo); in truncateVectorWithNARROW()
2691 Hi = DAG.getBitcast(InVT, Hi); in truncateVectorWithNARROW()
2711 EVT InVT = In.getValueType(); in performTruncateCombine() local
2712 if (!InVT.isSimple()) in performTruncateCombine()
2720 EVT InSVT = InVT.getVectorElementType(); in performTruncateCombine()
2727 APInt Mask = APInt::getLowBitsSet(InVT.getScalarSizeInBits(), in performTruncateCombine()
2729 In = DAG.getNode(ISD::AND, DL, InVT, In, DAG.getConstant(Mask, DL, InVT)); in performTruncateCombine()
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 278 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) { in MergeInTypeInfo()
279 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
281 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
282 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21988 InVT = EVT::getVectorVT(Ctx, InVT, 128 / InVT.getSizeInBits()); in truncateVectorWithPACK()
22001 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithPACK()
22075 assert((InVT.is256BitVector() || InVT.is128BitVector()) && in LowerTruncateVecI1()
22113 InVT = ExtVT; in LowerTruncateVecI1()
22141 if ((InVT == MVT::v8i64 || InVT == MVT::v16i32 || InVT == MVT::v16i64) && in LowerTRUNCATE()
31889 if (InVT == NVT) in ExtendToType()
32633 (InVT == MVT::v4i16 || InVT == MVT::v4i8)){ in ReplaceNodeResults()
32667 InVT = getTypeToTransformTo(*DAG.getContext(), InVT); in ReplaceNodeResults()
52642 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32 && in combineUIntToFP()
52705 if (InVT.isVector() && InVT.getScalarSizeInBits() < 32 && in combineSIntToFP()
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| H A D | X86InstrAVX512.td | 340 X86VectorVTInfo InVT,
345 !con((ins InVT.RC:$src1), NonTiedIns),
346 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
347 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
349 (vselect_mask InVT.KRCWM:$mask, RHS,
350 (bitconvert InVT.RC:$src1)),
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3763 InVT = InVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT()
3973 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
4427 EVT InVT = Op.getValueType(); in getSVEPredicateBitCast() local
4439 if (InVT == VT) in getSVEPredicateBitCast()
4448 if (InVT.bitsGT(VT)) in getSVEPredicateBitCast()
15972 EVT InVT = N0.getValueType(); in performVectorAddSubExtCombine() local
20101 EVT InVT = In.getValueType(); in ReplaceExtractSubVectorResults() local
20104 if (!InVT.isScalableVector() || !InVT.isInteger()) in ReplaceExtractSubVectorResults()
21860 InVT.isScalableVector() && isTypeLegal(InVT) && in getSVESafeBitCast()
21866 if (InVT == VT) in getSVESafeBitCast()
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| H A D | AArch64ISelDAGToDAG.cpp | 3596 EVT InVT = Node->getOperand(0).getValueType(); in Select() local
3597 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in Select()
3620 EVT InVT = Node->getOperand(1).getValueType(); in Select() local
3621 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1632 MVT InVT = V.getSimpleValueType(); in Select() local
1640 if (InVT.isFixedLengthVector()) in Select()
1641 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
1647 InVT, SubVecContainerVT, Idx, TRI); in Select()
1658 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
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| H A D | RISCVISelLowering.cpp | 6022 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
6023 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3510 EVT InVT = In.getValueType(); in lowerBITCAST() local
3525 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3541 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4770 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
4771 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
4781 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
5560 EVT InVT = PackedOp.getValueType(); in lowerSIGN_EXTEND_VECTOR_INREG() local
5562 unsigned FromBits = InVT.getScalarSizeInBits(); in lowerSIGN_EXTEND_VECTOR_INREG()
5579 EVT InVT = PackedOp.getValueType(); in lowerZERO_EXTEND_VECTOR_INREG() local
5585 DAG.getSplatVector(InVT, DL, DAG.getConstant(0, DL, InVT.getScalarType())); in lowerZERO_EXTEND_VECTOR_INREG()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2938 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
2939 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
2940 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3083 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3084 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3092 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5521 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5522 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5525 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5526 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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| H A D | PPCISelLowering.cpp | 8505 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8508 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
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