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Searched refs:INSERT_SUBVECTOR (Results 1 – 25 of 27) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-widen-scalable-vectortype.ll11 ; scalable-vector INSERT_SUBVECTOR and EXTRACT_SUBVECTOR is not yet available.
H A Dsve-fixed-length-subvector.ll8 ; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0
H A Dsve-insert-vector.ll298 ; This tests promotion of the input operand to INSERT_SUBVECTOR.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcanonicalize-vector-insert.ll5 ; scalable case, we lower to the INSERT_SUBVECTOR ISD node.
116 ; INSERT_SUBVECTOR ISD node later.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h558 INSERT_SUBVECTOR, enumerator
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp959 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1391 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
2991 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Lo, Idx); in SplitVecOp_INSERT_SUBVECTOR()
2993 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, FirstInsertion, Hi, in SplitVecOp_INSERT_SUBVECTOR()
3658 case ISD::INSERT_SUBVECTOR: in WidenVectorResult()
4233 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
4236 ISD::INSERT_SUBVECTOR, DL, WideResVT, DAG.getUNDEF(WideResVT), in WidenVecRes_OverflowOp()
5559 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT, in WidenVecOp_EXTEND()
5805 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, InVec, SubVec, in WidenVecOp_INSERT_SUBVECTOR()
6135 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Op, SplatNeutral, in WidenVecOp_VECREDUCE()
[all …]
H A DLegalizeVectorOps.cpp1013 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandANY_EXTEND_VECTOR_INREG()
1072 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcVT, DAG.getUNDEF(SrcVT), in ExpandZERO_EXTEND_VECTOR_INREG()
H A DSelectionDAGDumper.cpp293 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DDAGCombiner.cpp1789 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
20333 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
21291 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && in getSubVectorSrc()
21835 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
22648 TLI.isOperationLegalOrCustom(ISD::INSERT_SUBVECTOR, VT)) { in visitVECTOR_SHUFFLE()
23201 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23210 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
23212 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
23244 if (NewIdx && hasOperation(ISD::INSERT_SUBVECTOR, NewVT)) { in visitINSERT_SUBVECTOR()
23256 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
[all …]
H A DLegalizeIntegerTypes.cpp110 case ISD::INSERT_SUBVECTOR: in PromoteIntegerResult()
1672 case ISD::INSERT_SUBVECTOR: Res = PromoteIntOp_INSERT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5274 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx); in PromoteIntRes_INSERT_SUBVECTOR()
5527 SDValue Ext = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, PromVT, V0, V1, Idx); in PromoteIntOp_INSERT_SUBVECTOR()
5553 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op, in PromoteIntOp_CONCAT_VECTORS()
H A DTargetLowering.cpp850 case ISD::INSERT_SUBVECTOR: { in SimplifyMultipleUseDemandedBits()
1202 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedBits()
1381 if (Op0.getOpcode() == ISD::INSERT_SUBVECTOR && in SimplifyDemandedBits()
1396 TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, NewAnd, in SimplifyDemandedBits()
3038 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
3056 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in SimplifyDemandedVectorElts()
H A DSelectionDAG.cpp3033 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
4385 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
6293 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
6477 case ISD::INSERT_SUBVECTOR: { in getNode()
11363 return getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, getUNDEF(WideVT), N, in WidenVector()
H A DSelectionDAGBuilder.cpp626 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
7223 setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec, in visitIntrinsicCall()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1168 (Op.getOpcode() == ISD::INSERT_SUBVECTOR && in isTargetCanonicalConstantNode()
1170 Op = Op.getOperand(Op.getOpcode() == ISD::INSERT_SUBVECTOR ? 1 : 0); in isTargetCanonicalConstantNode()
H A DX86ISelLowering.cpp2330 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
6498 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
7401 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetConstantBitsFromNode()
8097 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetShuffleAndZeroables()
8286 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
8757 if (Opcode == ISD::INSERT_SUBVECTOR) { in getShuffleScalarElt()
14502 case ISD::INSERT_SUBVECTOR: { in lowerShuffleAsBroadcast()
16972 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128Shuffle()
18500 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128Shuffle()
19187 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lower1BitShuffle()
[all …]
H A DX86ISelDAGToDAG.cpp759 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
988 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
991 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
1016 CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, CurDAG->getUNDEF(VT), in PreprocessISelDAG()
1019 Res = CurDAG->getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, NarrowBCast, in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp493 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
603 {ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
3456 case ISD::INSERT_SUBVECTOR: in LowerOperation()
3487 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, Vec, SubVec, in LowerOperation()
5446 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ExtVecVT, Vec, SubVec, in lowerINSERT_SUBVECTOR()
5466 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, ContainerVT, in lowerINSERT_SUBVECTOR()
5540 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InterSubVT, in lowerINSERT_SUBVECTOR()
5550 Slideup = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, Vec, Slideup, in lowerINSERT_SUBVECTOR()
5755 ISD::INSERT_SUBVECTOR, DL, VecVT, Res, Lo, in lowerVECTOR_REVERSE()
5880 StoreVal = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerFixedLengthVectorStoreToRVV()
[all …]
H A DRISCVISelDAGToDAG.cpp1575 case ISD::INSERT_SUBVECTOR: { in Select()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp104 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
198 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
345 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
2447 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1645 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1695 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3200 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1153 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1233 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1289 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1354 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
5466 case ISD::INSERT_SUBVECTOR: in LowerOperation()
11693 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, HalfVT, Hi, Vec1, in LowerINSERT_SUBVECTOR()
19461 if (Insert.getOpcode() != ISD::INSERT_SUBVECTOR) in performDupLane128Combine()
19485 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, NewSubvecVT, in performDupLane128Combine()
19550 case ISD::INSERT_SUBVECTOR: in PerformDAGCombine()
[all …]
H A DAArch64ISelDAGToDAG.cpp689 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
3612 case ISD::INSERT_SUBVECTOR: { in Select()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td708 def vector_insert_subvec : SDNode<"ISD::INSERT_SUBVECTOR",
714 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp258 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
360 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
364 setOperationAction(ISD::INSERT_SUBVECTOR, in SITargetLowering()
523 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
4674 case ISD::INSERT_SUBVECTOR: in LowerOperation()
H A DAMDGPUISelLowering.cpp1480 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1483 HiVT.isVector() ? ISD::INSERT_SUBVECTOR : ISD::INSERT_VECTOR_ELT, SL, in SplitVectorLoad()

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