Lines Matching refs:INSERT_SUBVECTOR
919 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1537 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1639 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1870 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2005 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2125 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f16, Legal); in X86TargetLowering()
2166 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2330 ISD::INSERT_SUBVECTOR, in X86TargetLowering()
6443 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()
6468 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec, in widenSubVector()
6498 if (N->getOpcode() == ISD::INSERT_SUBVECTOR) { in collectConcatOps()
6515 if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && in collectConcatOps()
6755 Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6772 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, in insert1BitVector()
6777 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6784 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6822 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6827 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, in insert1BitVector()
6843 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx); in insert1BitVector()
7401 if (Op.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetConstantBitsFromNode()
8097 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in getTargetShuffleAndZeroables()
8286 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
8757 if (Opcode == ISD::INSERT_SUBVECTOR) { in getShuffleScalarElt()
9377 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), in EltsFromConsecutiveLoads()
11483 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, in LowerAVXCONCAT_VECTORS()
11531 SubVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ShiftVT, in LowerCONCAT_VECTORSvXi1()
11548 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec, in LowerCONCAT_VECTORSvXi1()
11567 SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, in LowerCONCAT_VECTORSvXi1()
11570 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1), in LowerCONCAT_VECTORSvXi1()
14502 case ISD::INSERT_SUBVECTOR: { in lowerShuffleAsBroadcast()
16972 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128Shuffle()
17001 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV2X128Shuffle()
17307 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V, in getShuffleHalfVectors()
17336 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi, in lowerShuffleWithUndefHalf()
17346 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi, in lowerShuffleWithUndefHalf()
17726 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v32i8, in lowerShuffleAsVTRUNCAndUnpack()
18500 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128Shuffle()
18514 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec, in lowerV4X128Shuffle()
19103 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, in lower1BitShuffleAsKSHIFTR()
19187 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lower1BitShuffle()
19206 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT, in lower1BitShuffle()
19707 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT, in ExtractBitFromMaskVector()
19894 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VecVT, Vec, EltInVec, Idx); in InsertBitToMaskVector()
20165 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVecVT, in LowerEXTRACT_SUBVECTOR()
20883 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i64, Tmp, Src, in lowerINT_TO_FP_vXi64()
21335 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideIntVT, Tmp, V, in lowerUINT_TO_FP_vXi32()
21901 In = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT, DAG.getUNDEF(InVT), in LowerZERO_EXTEND_Mask()
22361 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8f64, Tmp, Src, in LowerFP_TO_INT()
22460 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Tmp, Src, in LowerFP_TO_INT()
22490 Src = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Tmp, Src, in LowerFP_TO_INT()
25372 In = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, InVT, DAG.getUNDEF(InVT), in LowerSIGN_EXTEND_Mask()
25667 StoredVal = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1, in LowerStore()
26875 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1, in LowerINTRINSIC_WO_CHAIN()
26922 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1, in LowerINTRINSIC_WO_CHAIN()
26981 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v16i1, in LowerINTRINSIC_WO_CHAIN()
31930 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal, in ExtendToType()
32234 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG); in LowerOperation()
37972 if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR) in combineX86ShuffleChain()
38046 if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR) in combineX86ShuffleChain()
38060 if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR) in combineX86ShuffleChain()
40157 if (V.getOpcode() == ISD::INSERT_SUBVECTOR && V.getOperand(0).isUndef() && in combineTargetShuffle()
40165 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in combineTargetShuffle()
40275 if ((Idx & 1) == 1 && Src.getOpcode() == ISD::INSERT_SUBVECTOR && in combineTargetShuffle()
42588 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in combineBitcastToBoolVector()
44812 Cond = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, SrcCondVT, in combineSelect()
47284 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v16i1, in combineCompareEqual()
50942 N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.getOperand(0).isUndef() && in combineXor()
50945 ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in combineXor()
52023 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VecVT, in combineVectorSizedSetCCEquality()
54211 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineINSERT_SUBVECTOR()
54214 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineINSERT_SUBVECTOR()
54226 SubVec.getOperand(0).getOpcode() == ISD::INSERT_SUBVECTOR) { in combineINSERT_SUBVECTOR()
54232 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineINSERT_SUBVECTOR()
54278 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, in combineINSERT_SUBVECTOR()
54445 InVec.getOpcode() == ISD::INSERT_SUBVECTOR && InVec.hasOneUse() && in combineEXTRACT_SUBVECTOR()
54452 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, NewExt, in combineEXTRACT_SUBVECTOR()
55037 case ISD::INSERT_SUBVECTOR: in PerformDAGCombine()