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Searched refs:HasBaseReg (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp294 bool HasBaseReg = BaseReg.getReg() != 0; in PrintLeaMemReference() local
295 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintLeaMemReference()
297 HasBaseReg = false; in PrintLeaMemReference()
300 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in PrintLeaMemReference()
325 if (HasBaseReg) in PrintLeaMemReference()
392 bool HasBaseReg = BaseReg.getReg() != 0; in PrintIntelMemReference() local
393 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in PrintIntelMemReference()
395 HasBaseReg = false; in PrintIntelMemReference()
400 HasBaseReg = false; in PrintIntelMemReference()
412 if (HasBaseReg) { in PrintIntelMemReference()
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H A DX86ISelLowering.cpp33860 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
33882 if (AM.HasBaseReg) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp349 bool HasBaseReg = false; member
469 HasBaseReg = true; in initialMatch()
475 HasBaseReg = true; in initialMatch()
625 if (HasBaseReg && BaseRegs.empty()) { in print()
628 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1831 bool HasBaseReg) { in isAlwaysFoldable() argument
1841 if (!HasBaseReg && Scale == 1) { in isAlwaysFoldable()
1843 HasBaseReg = true; in isAlwaysFoldable()
1854 bool HasBaseReg) { in isAlwaysFoldable() argument
3420 F.HasBaseReg = true; in InsertSupplementalFormula()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h206 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
300 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
304 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
927 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
976 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, in getGEPCost()
H A DTargetTransformInfo.h622 bool HasBaseReg, int64_t Scale,
726 int64_t BaseOffset, bool HasBaseReg,
1584 int64_t BaseOffset, bool HasBaseReg,
1620 bool HasBaseReg, int64_t Scale,
1979 bool HasBaseReg, int64_t Scale, unsigned AddrSpace, in isLegalAddressingMode() argument
1981 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in isLegalAddressingMode()
2058 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
2061 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, in getScalingFactorCost()
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp351 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
354 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
464 Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
467 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); in getScalingFactorCost()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h309 bool HasBaseReg, int64_t Scale,
314 AM.HasBaseReg = HasBaseReg;
364 int64_t BaseOffset, bool HasBaseReg, in getScalingFactorCost() argument
369 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2517 bool HasBaseReg = false; member
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp262 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp2079 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
2104 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1259 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1317 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1336 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
9397 AM.HasBaseReg = true; in performSHLPtrCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp3530 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4672 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4677 AddrMode.HasBaseReg = true; in matchOperationAddr()
4688 if (AddrMode.HasBaseReg) in matchOperationAddr()
4690 AddrMode.HasBaseReg = true; in matchOperationAddr()
4824 if (!AddrMode.HasBaseReg) { in matchAddr()
4825 AddrMode.HasBaseReg = true; in matchAddr()
4830 AddrMode.HasBaseReg = false; in matchAddr()
H A DTargetLoweringBase.cpp1953 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1958 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp876 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp907 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
919 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp1375 AMNew.HasBaseReg = true; in matchPtrAddImmedChain()
1378 AMOld.HasBaseReg = true; in matchPtrAddImmedChain()
4492 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4369 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
4376 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1889 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4300 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp19335 if (!AM.HasBaseReg && Scale == 2) in isLegalT2ScaledAddressingMode()
19361 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); in isLegalT1ScaledAddressingMode()
19408 if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) in isLegalAddressingMode()
19411 if (!AM.HasBaseReg && Scale == 2) in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1041 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
1068 AM.HasBaseReg = true; in reassociationCanBreakAddressingModePattern()
2151 AM.HasBaseReg = true; in canFoldInAddressingMode()
2160 AM.HasBaseReg = true; in canFoldInAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1063 return AM.HasBaseReg && AM.Scale == 0 && !AM.BaseOffs; in isLegalAddressingMode()
1073 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16311 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
16316 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13539 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
13546 return AM.HasBaseReg && !AM.BaseOffs && in isLegalAddressingMode()