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Searched refs:GPR32RegClass (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
759 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
763 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
767 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
953 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
1026 RC = &Mips::GPR32RegClass; in selectSelect()
1605 R = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
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H A DMipsInstructionSelector.cpp128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
373 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
389 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
401 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
483 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
598 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
702 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
757 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
871 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
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H A DMipsMachineFunction.cpp51 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
81 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
162 : Mips::GPR32RegClass; in createEhDataRegsFI()
174 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI()
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
66 const MCRegisterClass *GPR32RegClass; variable
H A DMipsSEFrameLowering.cpp317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
590 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
719 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
753 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
893 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
909 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSERegisterInfo.cpp56 return &Mips::GPR32RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
332 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
628 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsISelLowering.cpp4136 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
4139 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
4781 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W()
4836 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D()
4837 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D()
4912 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitSTR_W()
4925 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitSTR_W()
4977 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitSTR_D()
4978 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitSTR_D()
5003 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitSTR_D()
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H A DMipsSubtarget.cpp235 : &Mips::GPR32RegClass); in getCriticalPathRCs()
H A DMips16InstrInfo.cpp76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp68 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
3029 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
3098 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3330 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3515 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitST_F16_PSEUDO()
3517 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitST_F16_PSEUDO()
3518 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO()
3570 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitLD_F16_PSEUDO()
3579 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitLD_F16_PSEUDO()
3660 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
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H A DMipsAsmPrinter.cpp337 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
356 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
H A DARCInstrInfo.cpp285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
287 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
H A DARCRegisterInfo.cpp60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in replaceFrameIndex()
207 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); in eliminateFrameIndex()
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
531 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
576 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
138 else if (RC == &BPF::GPR32RegClass) in storeRegToStackSlot()
158 else if (RC == &BPF::GPR32RegClass) in loadRegFromStackSlot()
H A DBPFISelLowering.cpp63 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
249 return std::make_pair(0U, &BPF::GPR32RegClass); in getRegForInlineAsmConstraint()
334 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
H A DBPFMISimplifyPatchable.cpp171 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
469 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
1711 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
2526 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2545 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2666 RC = &AArch64::GPR32RegClass; in selectSelect()
2958 RC = &AArch64::GPR32RegClass; in fastLowerArguments()
3922 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
4751 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4848 RC = &AArch64::GPR32RegClass; in selectSDiv()
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/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/AArch64/
H A DTarget.cpp46 if (AArch64::GPR32RegClass.contains(Reg)) in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp81 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp150 if (Mips::GPR32RegClass.contains(Reg)) in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp519 : &AArch64::GPR32RegClass; in getRegClassForTypeOnBank()
557 : &AArch64::GPR32RegClass; in getMinClassForRegBank()
2592 MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
2679 AArch64::GPR32RegClass, MRI); in select()
2714 AArch64::GPR32RegClass, MRI); in select()
3099 } else if (DstRC == &AArch64::GPR32RegClass && in select()
4593 const TargetRegisterClass *RC = &AArch64::GPR32RegClass; in emitCSetForFCmp()
5769 AArch64::GPR32RegClass, MRI); in selectIntrinsic()
5785 AArch64::GPR32RegClass, MRI); in selectIntrinsic()
6349 AArch64::GPR32RegClass, MIB); in selectAddrModeWRO()
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