519                           : &AArch64::GPR32RegClass;  in getRegClassForTypeOnBank()
557                           : &AArch64::GPR32RegClass;  in getMinClassForRegBank()
1512         TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass,  in emitTestBit()
2207       RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);  in earlySelect()
2592           MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in select()
2679                                  AArch64::GPR32RegClass, MRI);  in select()
2714                                  AArch64::GPR32RegClass, MRI);  in select()
2803           Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in select()
2927       Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in select()
3099       } else if (DstRC == &AArch64::GPR32RegClass &&  in select()
3246           Register OrDst = MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in select()
3263         if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass,  in select()
3277         if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass,  in select()
3353     Register DeadVReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in select()
4527   auto RC = Is32Bit ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass;  in emitCMN()
4593   const TargetRegisterClass *RC = &AArch64::GPR32RegClass;  in emitCSetForFCmp()
5287     Register NewReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);  in selectUSMovFromExtend()
5769                                    AArch64::GPR32RegClass, MRI);  in selectIntrinsic()
5785                                    AArch64::GPR32RegClass, MRI);  in selectIntrinsic()
6128     OffsetReg = moveScalarRegClass(OffsetReg, AArch64::GPR32RegClass, MIB);  in selectExtendedSHL()
6349                                        AArch64::GPR32RegClass, MIB);  in selectAddrModeWRO()
6692   ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB);  in selectArithExtendedRegister()