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Searched refs:FREM (Results 1 – 25 of 36) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfrem-msvc32.ll1 ; Make sure that 32-bit FREM is promoted to 64-bit FREM on 32-bit MSVC.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfpcast.ll115 ; CHECK-NEXT: [[FREM:%.*]] = frem <1 x double> [[V:%.*]], [[V]]
116 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <1 x double> [[FREM]] to <1 x float>
126 ; CHECK-NEXT: [[FREM:%.*]] = frem double [[V:%.*]], 1.000000e+00
127 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[FREM]] to float
138 ; CHECK-NEXT: [[FREM:%.*]] = frem double [[FEXT]], 1.000000e-01
139 ; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double [[FREM]] to float
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def56 DAG_INSTRUCTION(FRem, 2, 1, experimental_constrained_frem, FREM)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h394 FREM, enumerator
H A DTargetLowering.h2661 case ISD::FREM: in isBinOp()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h500 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
H A DSelectionDAGDumper.cpp268 case ISD::FREM: return "frem"; in getOperationName()
H A DLegalizeFloatTypes.cpp115 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult()
1276 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult()
2285 case ISD::FREM: in PromoteFloatResult()
2650 case ISD::FREM: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp330 case ISD::FREM: in LegalizeOp()
H A DFastISel.cpp1707 return selectBinaryOp(I, ISD::FREM); in selectOperator()
H A DLegalizeVectorTypes.cpp140 case ISD::FREM: in ScalarizeVectorResult()
1085 case ISD::FREM: case ISD::VP_FREM: in SplitVectorResult()
3745 case ISD::FREM: in WidenVectorResult()
H A DSelectionDAG.cpp4614 case ISD::FREM: in isKnownNeverNaN()
5793 case ISD::FREM: in foldConstantFPMath()
5831 case ISD::FREM: in foldConstantFPMath()
6018 case ISD::FREM: in getNode()
H A DLegalizeDAG.cpp4189 case ISD::FREM: in ConvertNodeToLibcall()
4751 case ISD::FREM: in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp117 ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN}; in CSKYTargetLowering()
124 setOperationAction(ISD::FREM, VT, Expand); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp606 case ISD::FREM: in getArithmeticInstrCost()
H A DAMDGPUISelLowering.cpp307 setOperationAction(ISD::FREM, {MVT::f16, MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
398 ISD::FEXP, ISD::FLOG2, ISD::FREM, ISD::FLOG, in AMDGPUTargetLowering()
546 case ISD::FREM: in hasSourceMods()
1155 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
H A DAMDGPUISelDAGToDAG.cpp146 case ISD::FREM: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1729 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1734 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1739 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1799 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1590 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1635 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp433 setOperationAction(ISD::FREM, MVT::f32, Expand); in MipsTargetLowering()
434 setOperationAction(ISD::FREM, MVT::f64, Expand); in MipsTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp228 setOperationAction(ISD::FREM, VT, Expand); in initSPUActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp417 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering()
418 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering()
419 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering()
439 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering()
590 for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI, in AArch64TargetLowering()
1324 setOperationAction(ISD::FREM, VT, Expand); in AArch64TargetLowering()
1505 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp203 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
363 setOperationAction(ISD::FREM, VT, Expand); in addMVEVectorTypes()
862 setOperationAction(ISD::FREM, MVT::v2f64, Expand); in ARMTargetLowering()
1038 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1441 setOperationAction(ISD::FREM, MVT::f64, Expand); in ARMTargetLowering()
1442 setOperationAction(ISD::FREM, MVT::f32, Expand); in ARMTargetLowering()
1517 setOperationAction(ISD::FREM, MVT::f16, Promote); in ARMTargetLowering()

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