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Searched refs:FP_TO_SINT_SAT (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h838 FP_TO_SINT_SAT, enumerator
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp154 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
173 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
254 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) in WebAssemblyTargetLowering()
1431 case ISD::FP_TO_SINT_SAT: in LowerOperation()
2512 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2550 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2595 case ISD::FP_TO_SINT_SAT: in performVectorTruncZeroCombine()
2744 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp410 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
850 case ISD::FP_TO_SINT_SAT: in Expand()
H A DSelectionDAGDumper.cpp360 case ISD::FP_TO_SINT_SAT: return "fp_to_sint_sat"; in getOperationName()
H A DLegalizeFloatTypes.cpp844 case ISD::FP_TO_SINT_SAT: in SoftenFloatOperand()
2114 case ISD::FP_TO_SINT_SAT: in PromoteFloatOperand()
2910 case ISD::FP_TO_SINT_SAT: in SoftPromoteHalfOperand()
H A DLegalizeVectorTypes.cpp170 case ISD::FP_TO_SINT_SAT: in ScalarizeVectorResult()
1113 case ISD::FP_TO_SINT_SAT: in SplitVectorResult()
2734 case ISD::FP_TO_SINT_SAT: in SplitVectorOperand()
3828 case ISD::FP_TO_SINT_SAT: in WidenVectorResult()
5468 case ISD::FP_TO_SINT_SAT: in WidenVectorOperand()
H A DLegalizeDAG.cpp1145 case ISD::FP_TO_SINT_SAT: in LegalizeOp()
2998 case ISD::FP_TO_SINT_SAT: in ExpandNode()
4522 case ISD::FP_TO_SINT_SAT: in PromoteNode()
H A DLegalizeIntegerTypes.cpp147 case ISD::FP_TO_SINT_SAT: in PromoteIntegerResult()
2428 case ISD::FP_TO_SINT_SAT: in ExpandIntegerResult()
H A DSelectionDAG.cpp4056 case ISD::FP_TO_SINT_SAT: in ComputeNumSignBits()
6131 case ISD::FP_TO_SINT_SAT: in getNode()
H A DTargetLowering.cpp9529 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in expandFP_TO_INT_SAT()
H A DSelectionDAGBuilder.cpp6416 setValue(&I, DAG.getNode(ISD::FP_TO_SINT_SAT, sdl, VT, in visitIntrinsicCall()
H A DDAGCombiner.cpp5138 unsigned NewOpc = Unsigned ? ISD::FP_TO_UINT_SAT : ISD::FP_TO_SINT_SAT; in PerformMinMaxFpToSatCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp809 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp491 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in AArch64TargetLowering()
492 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in AArch64TargetLowering()
878 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
971 ISD::FP_ROUND, ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, ISD::MUL, in AArch64TargetLowering()
1508 {ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in addTypeForNEON()
3892 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerVectorFP_TO_INT_SAT()
3948 if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { in LowerFP_TO_INT_SAT()
5505 case ISD::FP_TO_SINT_SAT: in LowerOperation()
14502 if (N->getOpcode() == ISD::FP_TO_SINT_SAT || in performFpToIntCombine()
14511 N->getOpcode() == ISD::FP_TO_SINT_SAT); in performFpToIntCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp381 setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT, in RISCVTargetLowering()
961 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}); in RISCVTargetLowering()
1799 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in lowerFP_TO_INT_SAT()
3414 case ISD::FP_TO_SINT_SAT: in LowerOperation()
8578 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT_SAT; in performFP_TO_INT_SATCombine()
9095 case ISD::FP_TO_SINT_SAT: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td516 def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp309 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in addMVEVectorTypes()
775 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom); in ARMTargetLowering()
777 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in ARMTargetLowering()
5904 bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
10360 case ISD::FP_TO_SINT_SAT: in LowerOperation()
10547 case ISD::FP_TO_SINT_SAT: in ReplaceNodeResults()
H A DARMISelDAGToDAG.cpp3768 case ISD::FP_TO_SINT_SAT: in Select()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp301 setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom); in X86TargetLowering()
305 setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom); in X86TargetLowering()
22736 bool IsSigned = Node->getOpcode() == ISD::FP_TO_SINT_SAT; in LowerFP_TO_INT_SAT()
32262 case ISD::FP_TO_SINT_SAT: in LowerOperation()