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Searched refs:FP_EXTEND (Results 1 – 25 of 35) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def57 DAG_INSTRUCTION(FPExt, 1, 0, experimental_constrained_fpext, FP_EXTEND)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h871 FP_EXTEND, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1813 { ISD::FP_EXTEND, MVT::nxv2f32, MVT::nxv2f16, 1}, in getCastInstrCost()
1814 { ISD::FP_EXTEND, MVT::nxv4f32, MVT::nxv4f16, 1}, in getCastInstrCost()
1815 { ISD::FP_EXTEND, MVT::nxv8f32, MVT::nxv8f16, 2}, in getCastInstrCost()
1818 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f16, 1}, in getCastInstrCost()
1819 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f16, 2}, in getCastInstrCost()
1820 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f16, 4}, in getCastInstrCost()
1823 { ISD::FP_EXTEND, MVT::nxv2f64, MVT::nxv2f32, 1}, in getCastInstrCost()
1824 { ISD::FP_EXTEND, MVT::nxv4f64, MVT::nxv4f32, 2}, in getCastInstrCost()
1825 { ISD::FP_EXTEND, MVT::nxv8f64, MVT::nxv8f32, 6}, in getCastInstrCost()
H A DAArch64ISelLowering.cpp452 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in AArch64TargetLowering()
673 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand); in AArch64TargetLowering()
905 setTargetDAGCombine(ISD::FP_EXTEND); in AArch64TargetLowering()
1315 setOperationAction(ISD::FP_EXTEND, VT, Custom); in AArch64TargetLowering()
1657 setOperationAction(ISD::FP_EXTEND, VT, Custom); in addTypeForFixedLengthSVE()
5442 case ISD::FP_EXTEND: in LowerOperation()
7733 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2); in LowerFCOPYSIGN()
8103 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in LowerSELECT_CC()
8104 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in LowerSELECT_CC()
19571 case ISD::FP_EXTEND: in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2906 case ISD::FP_EXTEND: in ExpandNode()
4351 case ISD::FP_EXTEND: { in ConvertNodeToLibcall()
4628 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4674 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4695 if (ExtOp != ISD::FP_EXTEND) in PromoteNode()
4707 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4734 unsigned ExtOp = ISD::FP_EXTEND; in PromoteNode()
4755 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
4756 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); in PromoteNode()
4784 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
[all …]
H A DLegalizeFloatTypes.cpp106 case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; in SoftenFloatResult()
522 Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); in SoftenFloatRes_FP_EXTEND()
725 auto ExtendNode = DAG.getNode(ISD::FP_EXTEND, dl, VT, NewL); in SoftenFloatRes_LOAD()
1250 case ISD::FP_EXTEND: ExpandFloatRes_FP_EXTEND(N, Lo, Hi); break; in ExpandFloatResult()
1527 Hi = DAG.getNode(ISD::FP_EXTEND, dl, NVT, N->getOperand(0)); in ExpandFloatRes_FP_EXTEND()
2117 case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break; in PromoteFloatOperand()
2176 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op); in PromoteFloatOp_FP_EXTEND()
2534 ISD::FP_EXTEND, DL, NVT, in PromoteFloatRes_XINT_TO_FP()
2914 case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break; in SoftPromoteHalfOperand()
H A DDAGCombiner.cpp14066 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14080 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14106 if (N02.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14132 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14167 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFADDForFMACombine()
14282 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14297 if (N1.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14316 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14341 if (N00.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
14426 if (N0.getOpcode() == ISD::FP_EXTEND) { in visitFSUBForFMACombine()
[all …]
H A DLegalizeVectorOps.cpp385 case ISD::FP_EXTEND: in LegalizeOp()
559 case ISD::FP_EXTEND: in Promote()
584 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j)); in Promote()
H A DSelectionDAGDumper.cpp349 case ISD::FP_EXTEND: return "fp_extend"; in getOperationName()
H A DLegalizeVectorTypes.cpp97 case ISD::FP_EXTEND: in ScalarizeVectorResult()
680 case ISD::FP_EXTEND: in ScalarizeVectorOperand()
777 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res) in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
878 SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), in ScalarizeVecOp_FP_EXTEND()
1029 case ISD::FP_EXTEND: in SplitVectorResult()
2743 case ISD::FP_EXTEND: in SplitVectorOperand()
3807 case ISD::FP_EXTEND: in WidenVectorResult()
5452 case ISD::FP_EXTEND: in WidenVectorOperand()
H A DSelectionDAG.cpp479 return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND; in getExtForLoadExtType()
1343 ? getNode(ISD::FP_EXTEND, DL, VT, Op) in getFPExtendOrRound()
4644 case ISD::FP_EXTEND: in isKnownNeverNaN()
5082 case ISD::FP_EXTEND: { in getNode()
5135 case ISD::FP_EXTEND: in getNode()
5184 case ISD::FP_EXTEND: in getNode()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp559 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
560 {ISD::FP_EXTEND, MVT::v8f32, MVT::v8f16, 3}, in getCastInstrCost()
629 (ISD == ISD::FP_EXTEND && SrcTy.getScalarType() == MVT::f32 && in getCastInstrCost()
634 {ISD::FP_EXTEND, MVT::v2f32, 2}, in getCastInstrCost()
635 {ISD::FP_EXTEND, MVT::v4f32, 4}}; in getCastInstrCost()
821 if (ISD == ISD::FP_ROUND || ISD == ISD::FP_EXTEND) { in getCastInstrCost()
H A DARMISelLowering.cpp950 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand); in ARMTargetLowering()
1021 ISD::FP_EXTEND, ISD::SELECT, ISD::SELECT_CC, in ARMTargetLowering()
1072 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in ARMTargetLowering()
1081 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom); in ARMTargetLowering()
7609 if (BV.getOperand(0).getOpcode() != ISD::FP_EXTEND || in LowerBuildVectorOfFPExt()
7620 return Trunc.getOpcode() == ISD::FP_EXTEND && in LowerBuildVectorOfFPExt()
10447 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); in LowerOperation()
18635 case ISD::FP_EXTEND: in PerformDAGCombine()
20580 SDValue Result = DAG.getNode(ISD::FP_EXTEND, in LowerFP_EXTEND()
20606 SrcVal = DAG.getNode(ISD::FP_EXTEND, Loc, DstVT, SrcVal); in LowerFP_EXTEND()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp289 case ISD::FP_EXTEND: in getCastInstrCost()
H A DRISCVISelLowering.cpp653 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
902 setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom); in RISCVTargetLowering()
3299 SDValue Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op.getOperand(0)); in LowerOperation()
3307 case ISD::FP_EXTEND: in LowerOperation()
4399 Op.getOpcode() == ISD::VP_FP_EXTEND || Op.getOpcode() == ISD::FP_EXTEND; in lowerVectorFPExtendOrRoundLike()
9111 if (In2.getOpcode() != ISD::FP_EXTEND && in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h507 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1071 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
1073 X86_INTRINSIC_DATA(avx512fp16_mask_vcvtph2psx_256, INTR_TYPE_1OP_MASK, ISD::FP_EXTEND, 0),
1075 ISD::FP_EXTEND, X86ISD::VFPEXT_SAE),
H A DX86TargetTransformInfo.cpp1789 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 }, in getCastInstrCost()
1790 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
2170 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, in getCastInstrCost()
2300 { ISD::FP_EXTEND, MVT::v4f64, MVT::v4f32, 1 }, in getCastInstrCost()
H A DX86ISelLowering.cpp634 setOperationAction(ISD::FP_EXTEND, MVT::f32, LibCall); in X86TargetLowering()
635 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); in X86TargetLowering()
808 setOperationAction(ISD::FP_EXTEND, MVT::f80, Custom); in X86TargetLowering()
2371 ISD::FP_EXTEND, in X86TargetLowering()
3298 } else if (Copy->getOpcode() != ISD::FP_EXTEND) in isUsedByReturnOnly()
22904 return DAG.getNode(ISD::FP_EXTEND, DL, VT, in LowerFP_EXTEND()
23255 Sign = DAG.getNode(ISD::FP_EXTEND, dl, VT, Sign); in LowerFCOPYSIGN()
32264 case ISD::FP_EXTEND: in LowerOperation()
33121 case ISD::FP_EXTEND: in ReplaceNodeResults()
54510 if (InOpcode == ISD::FP_EXTEND && in combineEXTRACT_SUBVECTOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp154 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Custom); in initializeHVXLowering()
157 setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Legal); in initializeHVXLowering()
2030 assert(Op->getOpcode() == ISD::FP_EXTEND); in LowerHvxFpExtend()
2470 case ISD::FP_EXTEND: return LowerHvxFpExtend(Op, DAG); in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1193 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1230 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in PPCTargetLowering()
1256 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
7987 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
7997 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8003 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8009 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8015 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
11057 assert(Op.getOpcode() == ISD::FP_EXTEND && in LowerFP_EXTEND()
11322 case ISD::FP_EXTEND: in ReplaceNodeResults()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp269 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand); in SITargetLowering()
600 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand); in SITargetLowering()
3192 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
4919 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0); in lowerFCMPIntrinsic()
4920 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1); in lowerFCMPIntrinsic()
5285 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) : in getFPExtOrFPRound()
10030 case ISD::FP_EXTEND: in isCanonicalized()
11207 Op1.getOpcode() != ISD::FP_EXTEND || in performFMACombine()
11208 Op2.getOpcode() != ISD::FP_EXTEND) in performFMACombine()
11232 if (FMAOp1.getOpcode() != ISD::FP_EXTEND || in performFMACombine()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll4 ; FP_EXTEND
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1826 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1854 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
3170 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
1989 case ISD::FP_EXTEND: in LowerConvertLow()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1821 case FPExt: return ISD::FP_EXTEND; in InstructionOpcodeToISD()

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