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Searched refs:FPOW (Results 1 – 25 of 27) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def90 DAG_FUNCTION(pow, 2, 1, experimental_constrained_pow, FPOW)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h918 FPOW, enumerator
H A DBasicTTIImpl.h1751 ISD = ISD::FPOW; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp274 case ISD::FPOW: return "fpow"; in getOperationName()
H A DLegalizeFloatTypes.cpp111 case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break; in SoftenFloatResult()
1252 case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break; in ExpandFloatResult()
2284 case ISD::FPOW: in PromoteFloatResult()
2649 case ISD::FPOW: in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp4120 SDValue FPOW = in ConvertNodeToLibcall() local
4124 Results.push_back(FPOW); in ConvertNodeToLibcall()
4125 Results.push_back(FPOW.getValue(1)); in ConvertNodeToLibcall()
4130 Results.push_back(DAG.getNode(ISD::FPOW, SDLoc(Node), in ConvertNodeToLibcall()
4150 case ISD::FPOW: in ConvertNodeToLibcall()
4754 case ISD::FPOW: in PromoteNode()
H A DLegalizeVectorOps.cpp371 case ISD::FPOW: in LegalizeOp()
H A DLegalizeVectorTypes.cpp139 case ISD::FPOW: in ScalarizeVectorResult()
1076 case ISD::FPOW: in SplitVectorResult()
3744 case ISD::FPOW: in WidenVectorResult()
H A DDAGCombiner.cpp1762 case ISD::FPOW: return visitFPOW(N); in visit()
15508 (!DAG.getTargetLoweringInfo().isOperationExpand(ISD::FPOW, VT) && in visitFPOW()
H A DSelectionDAG.cpp4666 case ISD::FPOW: { in isKnownNeverNaN()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1749 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1750 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1751 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp117 ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN}; in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1591 ISD::FPOW, ISD::FCOPYSIGN}) { in HexagonTargetLowering()
1636 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp386 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
391 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
398 setOperationAction(ISD::FPOW , MVT::f64, Custom); in PPCTargetLowering()
404 setOperationAction(ISD::FPOW , MVT::f32, Custom); in PPCTargetLowering()
857 setOperationAction(ISD::FPOW, VT, Expand); in PPCTargetLowering()
1168 setOperationAction(ISD::FPOW, MVT::f128, Expand); in PPCTargetLowering()
11136 case ISD::FPOW: return lowerPow(Op, DAG); in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp296 setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, in AMDGPUTargetLowering()
399 ISD::FLOG10, ISD::FPOW, ISD::FFLOOR, ISD::FTRUNC, in AMDGPUTargetLowering()
H A DAMDGPUISelDAGToDAG.cpp157 case ISD::FPOW: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp425 setOperationAction(ISD::FPOW, MVT::f32, Expand); in MipsTargetLowering()
426 setOperationAction(ISD::FPOW, MVT::f64, Expand); in MipsTargetLowering()
H A DMipsSEISelLowering.cpp143 setOperationAction(ISD::FPOW, MVT::f16, Promote); in MipsSETargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp367 setOperationAction(ISD::FPOW, VT, Expand); in addMVEVectorTypes()
876 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); in ARMTargetLowering()
897 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); in ARMTargetLowering()
913 setOperationAction(ISD::FPOW, MVT::v2f32, Expand); in ARMTargetLowering()
1046 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
1448 setOperationAction(ISD::FPOW, MVT::f64, Expand); in ARMTargetLowering()
1449 setOperationAction(ISD::FPOW, MVT::f32, Expand); in ARMTargetLowering()
1523 setOperationAction(ISD::FPOW, MVT::f16, Promote); in ARMTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td493 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp438 setOperationAction(ISD::FPOW, MVT::f128, Expand); in AArch64TargetLowering()
581 setOperationAction(ISD::FPOW, MVT::f32, Expand); in AArch64TargetLowering()
582 setOperationAction(ISD::FPOW, MVT::f64, Expand); in AArch64TargetLowering()
590 for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI, in AArch64TargetLowering()
1325 setOperationAction(ISD::FPOW, VT, Expand); in AArch64TargetLowering()
1466 setOperationAction(ISD::FPOW, VT, Expand); in addTypeForNEON()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp316 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in RISCVTargetLowering()
333 ISD::FPOW, ISD::FPOWI, ISD::FCOS, ISD::FSIN, in RISCVTargetLowering()
669 setOperationAction(ISD::FPOW, VT, Expand); in RISCVTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp572 setOperationAction(ISD::FPOW, VT, Action); in X86TargetLowering()
878 setOperationAction(ISD::FPOW , MVT::f32 , Expand); in X86TargetLowering()
879 setOperationAction(ISD::FPOW , MVT::f64 , Expand); in X86TargetLowering()
880 setOperationAction(ISD::FPOW , MVT::f80 , Expand); in X86TargetLowering()
881 setOperationAction(ISD::FPOW , MVT::f128 , Expand); in X86TargetLowering()
900 setOperationAction(ISD::FPOW, VT, Expand); in X86TargetLowering()
2319 ISD::FPOW, ISD::STRICT_FPOW, in X86TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp472 setOperationAction(ISD::FPOW, VT, Expand); in SystemZTargetLowering()

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