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Searched refs:FNEARBYINT (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-nearbyint.mir19 ; FP16: $d0 = COPY [[FNEARBYINT]](<4 x s16>)
59 ; FP16: $q0 = COPY [[FNEARBYINT]](<8 x s16>)
111 ; FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
117 ; NO-FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
138 ; FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
144 ; NO-FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
165 ; FP16: $s0 = COPY [[FNEARBYINT]](s32)
171 ; NO-FP16: $s0 = COPY [[FNEARBYINT]](s32)
192 ; FP16: $d0 = COPY [[FNEARBYINT]](s64)
198 ; NO-FP16: $d0 = COPY [[FNEARBYINT]](s64)
[all …]
H A Dregbank-nearbyint.mir18 ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(<4 x s16>) = G_FNEARBYINT [[COPY]]
19 ; CHECK: $d0 = COPY [[FNEARBYINT]](<4 x s16>)
41 ; CHECK: $q0 = COPY [[FNEARBYINT]](<8 x s16>)
63 ; CHECK: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
85 ; CHECK: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
106 ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s32) = G_FNEARBYINT [[COPY]]
107 ; CHECK: $s0 = COPY [[FNEARBYINT]](s32)
128 ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s64) = G_FNEARBYINT [[COPY]]
129 ; CHECK: $d0 = COPY [[FNEARBYINT]](s64)
150 ; CHECK: [[FNEARBYINT:%[0-9]+]]:fpr(s16) = G_FNEARBYINT [[COPY]]
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def89 DAG_FUNCTION(nearbyint, 1, 1, experimental_constrained_nearbyint, FNEARBYINT)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h927 FNEARBYINT, enumerator
H A DBasicTTIImpl.h1739 ISD = ISD::FNEARBYINT; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp504 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
602 Opcode = ISD::FNEARBYINT; break; in mightUseCTR()
H A DPPCISelLowering.cpp309 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
846 setOperationAction(ISD::FNEARBYINT, VT, Expand); in PPCTargetLowering()
908 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
999 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
1000 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
1006 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
1012 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1207 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-foldable-fneg.mir317 ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FNEG]]
318 ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](s32)
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp210 case ISD::FNEARBYINT: return "fnearbyint"; in getOperationName()
H A DLegalizeFloatTypes.cpp103 case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; in SoftenFloatResult()
1247 case ISD::FNEARBYINT: ExpandFloatRes_FNEARBYINT(N, Lo, Hi); break; in ExpandFloatResult()
2266 case ISD::FNEARBYINT: in PromoteFloatResult()
2630 case ISD::FNEARBYINT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp380 case ISD::FNEARBYINT: in LegalizeOp()
H A DLegalizeVectorTypes.cpp93 case ISD::FNEARBYINT: in ScalarizeVectorResult()
1025 case ISD::FNEARBYINT: in SplitVectorResult()
3842 case ISD::FNEARBYINT: in WidenVectorResult()
H A DLegalizeDAG.cpp4085 case ISD::FNEARBYINT: in ConvertNodeToLibcall()
4837 case ISD::FNEARBYINT: in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp305 setOperationAction(ISD::FNEARBYINT, {MVT::f32, MVT::f64}, Custom); in AMDGPUTargetLowering()
400 ISD::FMUL, ISD::FMA, ISD::FRINT, ISD::FNEARBYINT, in AMDGPUTargetLowering()
510 case ISD::FNEARBYINT: in fnegFoldsIntoOp()
1159 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG); in LowerOperation()
3847 case ISD::FNEARBYINT: // XXX - Should fround be handled? in performFNegCombine()
H A DAMDGPUISelDAGToDAG.cpp166 case ISD::FNEARBYINT: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-rounding.ll128 ; FNEARBYINT
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp608 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
650 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand); in AArch64TargetLowering()
661 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand); in AArch64TargetLowering()
678 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
957 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1104 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1308 setOperationAction(ISD::FNEARBYINT, VT, Custom); in AArch64TargetLowering()
1655 setOperationAction(ISD::FNEARBYINT, VT, Custom); in addTypeForFixedLengthSVE()
5425 case ISD::FNEARBYINT: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp129 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1140 case ISD::FNEARBYINT: in PreprocessISelDAG()
1158 case ISD::FNEARBYINT: Imm = 0xC; break; in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp460 setOperationAction(ISD::FNEARBYINT, VT, Legal); in SystemZTargetLowering()
520 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in SystemZTargetLowering()
552 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp373 setOperationAction(ISD::FNEARBYINT, VT, Expand); in addMVEVectorTypes()
886 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); in ARMTargetLowering()
906 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in ARMTargetLowering()
922 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand); in ARMTargetLowering()
1055 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); in ARMTargetLowering()
1492 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in ARMTargetLowering()
1508 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in ARMTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td499 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1638 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp142 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in MipsSETargetLowering()

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