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Searched refs:FFLOOR (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-ffloor.mir18 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[COPY]]
19 ; SI-NEXT: $vgpr0 = COPY [[FFLOOR]](s32)
24 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[COPY]]
25 ; VI-NEXT: $vgpr0 = COPY [[FFLOOR]](s32)
31 ; GFX9-NEXT: $vgpr0 = COPY [[FFLOOR]](s32)
60 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
66 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
94 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
100 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
130 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FFLOOR]](s64)
[all …]
H A Dinst-select-ffloor.s16.mir19 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:sreg_32(s16) = G_FFLOOR [[TRUNC]]
20 ; VI-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FFLOOR]](s16)
90 ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
91 ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)
H A Dlegalize-fptoui.mir239 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
241 ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s64)
301 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
303 ; VI-NEXT: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s64)
391 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
424 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
438 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
464 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
487 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
673 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
[all …]
H A Dlegalize-fptosi.mir239 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
241 ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
301 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
303 ; VI-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
391 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
427 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
450 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
485 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
525 ; VI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
728 ; SI-NEXT: [[FFLOOR:%[0-9]+]]:_(s32) = G_FFLOOR [[FMUL]]
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def76 DAG_FUNCTION(floor, 1, 0, experimental_constrained_floor, FFLOOR)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h930 FFLOOR, enumerator
H A DBasicTTIImpl.h1730 ISD = ISD::FFLOOR; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp498 case Intrinsic::floor: Opcode = ISD::FFLOOR; break; in mightUseCTR()
598 Opcode = ISD::FFLOOR; break; in mightUseCTR()
H A DPPCISelLowering.cpp305 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
443 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
448 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
842 setOperationAction(ISD::FFLOOR, VT, Expand); in PPCTargetLowering()
905 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1003 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1205 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp204 case ISD::FFLOOR: return "ffloor"; in getOperationName()
H A DLegalizeFloatTypes.cpp91 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1235 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
2262 case ISD::FFLOOR: in PromoteFloatResult()
2626 case ISD::FFLOOR: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp383 case ISD::FFLOOR: in LegalizeOp()
H A DLegalizeVectorTypes.cpp89 case ISD::FFLOOR: in ScalarizeVectorResult()
1021 case ISD::FFLOOR: in SplitVectorResult()
3838 case ISD::FFLOOR: in WidenVectorResult()
H A DLegalizeDAG.cpp4067 case ISD::FFLOOR: in ConvertNodeToLibcall()
4834 case ISD::FFLOOR: in PromoteNode()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-rounding.ll66 ; FFLOOR
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp297 ISD::FFLOOR, ISD::FRINT, ISD::FTRUNC, ISD::FMINNUM, in AMDGPUTargetLowering()
399 ISD::FLOG10, ISD::FPOW, ISD::FFLOOR, ISD::FTRUNC, in AMDGPUTargetLowering()
1161 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
2560 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
H A DR600ISelLowering.cpp103 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR}, in R600TargetLowering()
H A DAMDGPUISelDAGToDAG.cpp168 case ISD::FFLOOR: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp331 setOperationAction({ISD::FREM, ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, in RISCVTargetLowering()
662 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
904 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
1848 } else if (Op.getOpcode() == ISD::FFLOOR) { in lowerFTRUNC_FCEIL_FFLOOR()
3419 case ISD::FFLOOR: in LowerOperation()
8488 case ISD::FFLOOR: return RISCVFPRndMode::RDN; in matchRoundingOp()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp608 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
647 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand); in AArch64TargetLowering()
658 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand); in AArch64TargetLowering()
678 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
957 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1104 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1307 setOperationAction(ISD::FFLOOR, VT, Custom); in AArch64TargetLowering()
1648 setOperationAction(ISD::FFLOOR, VT, Custom); in addTypeForFixedLengthSVE()
5423 case ISD::FFLOOR: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp129 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1134 case ISD::FFLOOR: in PreprocessISelDAG()
1152 case ISD::FFLOOR: Imm = 0x9; break; in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp461 setOperationAction(ISD::FFLOOR, VT, Legal); in SystemZTargetLowering()
521 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in SystemZTargetLowering()
553 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td498 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;

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