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Searched refs:FCEIL (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fceil.mir21 ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
31 ; CI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
40 ; VI-NEXT: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
68 ; SI-NEXT: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[COPY]]
69 ; SI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
75 ; CI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
81 ; VI-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
87 ; GFX9-NEXT: $vgpr0 = COPY [[FCEIL]](s32)
136 ; CI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
142 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
[all …]
H A Dregbankselect-fceil.mir17 ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
33 ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
H A Dinst-select-fceil.s16.mir19 ; GCN-NEXT: [[FCEIL:%[0-9]+]]:sreg_32(s16) = G_FCEIL [[TRUNC]]
20 ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FCEIL]](s16)
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def72 DAG_FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h924 FCEIL, enumerator
H A DBasicTTIImpl.h1733 ISD = ISD::FCEIL; in getTypeBasedIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp499 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
606 Opcode = ISD::FCEIL; break; in mightUseCTR()
H A DPPCISelLowering.cpp306 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
444 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
449 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
843 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
906 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
1004 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1206 setOperationAction(ISD::FCEIL, MVT::f128, Legal); in PPCTargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp206 case ISD::FCEIL: return "fceil"; in getOperationName()
H A DLegalizeFloatTypes.cpp80 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1224 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
2258 case ISD::FCEIL: in PromoteFloatResult()
2622 case ISD::FCEIL: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp377 case ISD::FCEIL: in LegalizeOp()
H A DLegalizeVectorTypes.cpp85 case ISD::FCEIL: in ScalarizeVectorResult()
1017 case ISD::FCEIL: in SplitVectorResult()
3834 case ISD::FCEIL: in WidenVectorResult()
H A DLegalizeDAG.cpp4073 case ISD::FCEIL: in ConvertNodeToLibcall()
4835 case ISD::FCEIL: in PromoteNode()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fp-rounding.ll4 ; FCEIL
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp296 setOperationAction({ISD::FCEIL, ISD::FEXP2, ISD::FPOW, ISD::FLOG2, ISD::FABS, in AMDGPUTargetLowering()
397 ISD::FCEIL, ISD::FCOS, ISD::FDIV, ISD::FEXP2, in AMDGPUTargetLowering()
1156 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
H A DR600ISelLowering.cpp103 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FRINT, ISD::FFLOOR}, in R600TargetLowering()
H A DAMDGPUISelDAGToDAG.cpp163 case ISD::FCEIL: in fp16SrcZerosHighBits()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp888 ISD::FEXP2, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp331 setOperationAction({ISD::FREM, ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, in RISCVTargetLowering()
662 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
904 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND}, in RISCVTargetLowering()
1839 if (Op.getOpcode() == ISD::FCEIL) { in lowerFTRUNC_FCEIL_FFLOOR()
3418 case ISD::FCEIL: in LowerOperation()
8489 case ISD::FCEIL: return RISCVFPRndMode::RUP; in matchRoundingOp()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp607 ISD::FNEG, ISD::FABS, ISD::FCEIL, in AArch64TargetLowering()
648 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); in AArch64TargetLowering()
655 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
678 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
956 ISD::FNEG, ISD::FABS, ISD::FCEIL, in AArch64TargetLowering()
1104 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1306 setOperationAction(ISD::FCEIL, VT, Custom); in AArch64TargetLowering()
1646 setOperationAction(ISD::FCEIL, VT, Custom); in addTypeForFixedLengthSVE()
5421 case ISD::FCEIL: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp129 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1132 case ISD::FCEIL: in PreprocessISelDAG()
1150 case ISD::FCEIL: Imm = 0xA; break; in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp462 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
522 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in SystemZTargetLowering()
554 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in SystemZTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td497 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp883 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
903 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
919 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
1052 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
1489 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
1505 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()

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