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Searched refs:DstVT (Results 1 – 25 of 35) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td2000 ValueType DstVT> {
2019 !if(!eq(DstVT.Size, 1),
2044 !if(!eq(DstVT.Size, 1),
2053 !if(!eq(DstVT.Size, 1),
2149 !if(!eq(DstVT.Size, 1),
2177 !if(!eq(DstVT.Size, 1),
2281 !if(!eq(DstVT.Size, 64),
2298 !if(!eq(DstVT.Size, 64),
2358 bit ret = !if(!eq(DstVT.Size, 64),
2386 field ValueType DstVT = ArgVT[0];
[all …]
H A DVOPInstructions.td1076 list<dag> ret3 = [(set P.DstVT:$vdst,
1081 list<dag> ret2 = [(set P.DstVT:$vdst,
1085 list<dag> ret1 = [(set P.DstVT:$vdst,
1101 list<dag> ret3 = [(set P.DstVT:$vdst,
1106 list<dag> ret2 = [(set P.DstVT:$vdst,
1111 list<dag> ret1 = [(set P.DstVT:$vdst,
1122 list<dag> ret3 = [(set P.DstVT:$vdst,
1127 list<dag> ret2 = [(set P.DstVT:$vdst,
1131 list<dag> ret1 = [(set P.DstVT:$vdst,
1140 list<dag> ret3 = [(set P.DstVT:$vdst,
[all …]
H A DVOP3PInstructions.td462 bit NoDstOverlap = !gt(DstVT.Size, 128);
469 let Src2VT = DstVT;
738 GCNPat < (P.DstVT (node
743 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, $src2_mod…
747 GCNPat < (P.DstVT (node
752 …(P.DstVT (Inst (i32 8), P.Src0VT:$src0, (i32 8), P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$sr…
756 GCNPat < (P.DstVT (node
761 …(P.DstVT (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, (i32 8), …
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
103 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
105 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
107 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP3Instructions.td108 let HasOMod = !ne(DstVT.Value, f16.Value);
801 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
802 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
803 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp1240 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1242 if (SrcVT != DstVT) { in X86SelectRet()
1539 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1557 if (DstVT == MVT::i64) { in X86SelectZExt()
1584 } else if (DstVT != MVT::i8) { in X86SelectZExt()
1597 if (!TLI.isTypeLegal(DstVT)) in X86SelectSExt()
1620 if (DstVT == MVT::i16) { in X86SelectSExt()
2522 if (DstVT != MVT::i8 && DstVT != MVT::i1) in X86SelectTrunc()
3625 if (DstVT.bitsGT(SrcVT)) in fastSelectInstruction()
3627 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
[all …]
H A DX86SelectionDAGInfo.cpp249 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
253 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp6694 MVT DstVT = VT; in getAVX512Node() local
12300 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
12303 DstVT = MVT::getVectorVT(DstVT, 128 / EltSizeInBits); in matchShuffleAsVTRUNC()
12352 if (DstVT != TruncVT) in getAVX512TruncNode()
21549 (DstVT == MVT::f32 || DstVT == MVT::f64)) in LowerUINT_TO_FP()
21957 if (SrcVT == DstVT) in truncateVectorWithPACK()
22747 EVT TmpVT = DstVT; in LowerFP_TO_INT_SAT()
37304 DstVT = MVT::getVectorVT(DstVT, NumDstElts); in matchUnaryShuffle()
37587 DstVT = MaskVT; in matchBinaryShuffle()
42445 !(DstVT.isVector() && DstVT.getVectorElementType() == MVT::i1 && in combineCastedMaskArithmetic()
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H A DX86ISelDAGToDAG.cpp1280 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1283 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1291 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1307 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1318 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1336 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1339 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1347 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1392 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
1403 assert(DstVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7435 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7439 (ins DstVT.FRC:$src1, SrcRC:$src),
7444 (ins DstVT.FRC:$src1, x86memop:$src),
7449 (ins DstVT.RC:$src1, SrcRC:$src2),
7451 [(set DstVT.RC:$dst,
7452 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
7458 [(set DstVT.RC:$dst,
7459 (OpNode (DstVT.VT DstVT.RC:$src1),
7477 [(set DstVT.RC:$dst,
7478 (OpNode (DstVT.VT DstVT.RC:$src1),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1064 MVT DstVT; in SelectIToFP() local
1066 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1069 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1090 if (DstVT == MVT::f32) in SelectIToFP()
1113 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1135 if (DstVT == MVT::f32) in SelectIToFP()
1189 MVT DstVT, SrcVT; in SelectFPToI() local
1191 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1194 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1236 if (DstVT == MVT::i32) in SelectFPToI()
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp743 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local
745 if (!DstVT || !SrcVT) in visitBitCastInst()
748 unsigned DstNumElems = cast<FixedVectorType>(DstVT)->getNumElements(); in visitBitCastInst()
757 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
763 auto *MidTy = FixedVectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
789 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp685 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
686 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
694 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
715 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
832 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
7331 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
7405 EVT DstVT = Node->getValueType(0); in expandFP_TO_UINT() local
7414 if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) || in expandFP_TO_UINT()
7510 EVT DstVT = Node->getValueType(0); in expandUINT_TO_FP() local
8204 EVT DstVT = LD->getValueType(0); in scalarizeVectorLoad() local
[all …]
H A DFastISel.cpp1379 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1381 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1382 !DstVT.isSimple()) in selectCast()
1387 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1399 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1417 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1423 if (SrcVT == DstVT) { in selectBitCast()
1429 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1784 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
1785 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h365 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
367 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
H A DRISCVISelLowering.cpp1796 EVT DstVT = Op.getValueType(); in lowerFP_TO_INT_SAT() local
1801 if (SatVT == DstVT) in lowerFP_TO_INT_SAT()
1811 Opc, DL, DstVT, Src, in lowerFP_TO_INT_SAT()
6335 if (DstVT.isFixedLengthVector()) { in lowerVPFPIntConvOp()
6336 DstVT = getContainerForFixedLengthVector(DstVT); in lowerVPFPIntConvOp()
6398 MVT InterimFVT = DstVT; in lowerVPFPIntConvOp()
6407 if (InterimFVT != DstVT) { in lowerVPFPIntConvOp()
6439 while (InterimIVT != DstVT) { in lowerVPFPIntConvOp()
8558 EVT DstVT = N->getValueType(0); in performFP_TO_INT_SATCombine() local
8559 if (DstVT != XLenVT) in performFP_TO_INT_SATCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3606 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3608 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3666 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3674 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3679 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3683 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3687 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3689 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3698 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3702 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
[all …]
H A DMipsFastISel.cpp1093 MVT DstVT, SrcVT; in selectFPToInt() local
1098 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1101 if (DstVT != MVT::i32) in selectFPToInt()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2655 static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL, in truncateVectorWithNARROW() argument
2660 if (SrcVT == DstVT) in truncateVectorWithNARROW()
2667 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation"); in truncateVectorWithNARROW()
2668 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation"); in truncateVectorWithNARROW()
2689 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) { in truncateVectorWithNARROW()
2693 return DAG.getBitcast(DstVT, Res); in truncateVectorWithNARROW()
2703 return truncateVectorWithNARROW(DstVT, Res, DL, DAG); in truncateVectorWithNARROW()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1528 MVT DstVT; in SelectIToFP() local
1530 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1573 MVT DstVT; in SelectFPToI() local
1575 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp6147 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
6180 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
6201 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
6204 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
6208 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
6211 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
18275 EVT DstVT = N->getValueType(0); in PerformBITCASTCombine() local
18905 !DstVT.isInteger()) in isTruncateFree()
18908 unsigned DestBits = DstVT.getSizeInBits(); in isTruncateFree()
20609 LC = RTLIB::getFPEXT(SrcVT, DstVT); in LowerFP_EXTEND()
[all …]
H A DARMISelLowering.h454 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1386 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1409 DstVT = MVT::i32; in tryIndexedLoad()
1413 if (DstVT == MVT::i64) in tryIndexedLoad()
1419 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1422 DstVT = MVT::i32; in tryIndexedLoad()
1426 if (DstVT == MVT::i64) in tryIndexedLoad()
1432 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1435 DstVT = MVT::i32; in tryIndexedLoad()
1456 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
H A DAArch64TargetTransformInfo.cpp1900 auto DstVT = TLI->getValueType(DL, Dst); in getExtractWithExtendCost() local
1907 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT)) in getExtractWithExtendCost()
1913 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
1929 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1295 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1298 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1303 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
1311 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1313 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1316 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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