| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 1514 APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts() local
1528 DemandedRHS.clearBit(i); in SimplifyDemandedVectorElts()
1533 simplifyAndSetOp(I, 2, DemandedRHS, UndefElts3); in SimplifyDemandedVectorElts()
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| /llvm-project-15.0.7/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 168 APInt &DemandedLHS, APInt &DemandedRHS) { in getShuffleDemandedElts() argument
177 DemandedLHS = DemandedRHS = APInt::getZero(NumElts); in getShuffleDemandedElts()
198 DemandedRHS.setBit(M % NumElts); in getShuffleDemandedElts()
1777 APInt DemandedLHS, DemandedRHS; in computeKnownBitsFromOperator() local
1778 if (!getShuffleDemandedElts(Shuf, DemandedElts, DemandedLHS, DemandedRHS)) { in computeKnownBitsFromOperator()
1791 if (!!DemandedRHS) { in computeKnownBitsFromOperator()
1793 computeKnownBits(RHS, DemandedRHS, Known2, Depth + 1, Q); in computeKnownBitsFromOperator()
3323 APInt DemandedLHS, DemandedRHS; in ComputeNumSignBitsImpl() local
3326 if (!getShuffleDemandedElts(Shuf, DemandedElts, DemandedLHS, DemandedRHS)) in ComputeNumSignBitsImpl()
3337 if (!!DemandedRHS) { in ComputeNumSignBitsImpl()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 2621 APInt DemandedRHS = APInt::getNullValue(NumElts); in isSplatValue() local
2634 DemandedRHS.setBit(M - NumElts); in isSplatValue()
2639 if ((DemandedLHS.isZero() && DemandedRHS.isZero()) || in isSplatValue()
2640 (!DemandedLHS.isZero() && !DemandedRHS.isZero())) in isSplatValue()
2654 return CheckSplatSrc(V.getOperand(1), DemandedRHS); in isSplatValue()
2974 APInt DemandedLHS(NumElts, 0), DemandedRHS(NumElts, 0); in computeKnownBits() local
2988 DemandedRHS.clearAllBits(); in computeKnownBits()
2995 DemandedRHS.setBit((unsigned)M % NumElts); in computeKnownBits()
3006 if (!!DemandedRHS) { in computeKnownBits()
3996 DemandedRHS.setBit((unsigned)M % NumElts); in ComputeNumSignBits()
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| H A D | TargetLowering.cpp | 1293 APInt DemandedRHS(NumElts, 0); in SimplifyDemandedBits() local
1302 DemandedRHS.clearAllBits(); in SimplifyDemandedBits()
1309 DemandedRHS.setBit(M - NumElts); in SimplifyDemandedBits()
1312 if (!!DemandedLHS || !!DemandedRHS) { in SimplifyDemandedBits()
1324 if (!!DemandedRHS) { in SimplifyDemandedBits()
1325 if (SimplifyDemandedBits(Op1, DemandedBits, DemandedRHS, Known2, TLO, in SimplifyDemandedBits()
1335 Op1, DemandedBits, DemandedRHS, TLO.DAG, Depth + 1); in SimplifyDemandedBits()
3155 APInt DemandedRHS(DemandedElts); in SimplifyDemandedVectorElts() local
3183 APInt DemandedRHS(NumElts, 0); in SimplifyDemandedVectorElts() local
3192 DemandedRHS.setBit(M - NumElts); in SimplifyDemandedVectorElts()
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| H A D | DAGCombiner.cpp | 22714 APInt DemandedRHS = APInt::getNullValue(NumElts); in visitVECTOR_SHUFFLE() local
22722 APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS; in visitVECTOR_SHUFFLE()
22728 (!DemandedLHS.isNullValue() || !DemandedRHS.isNullValue()) && in visitVECTOR_SHUFFLE()
22731 (DemandedRHS.isNullValue() || in visitVECTOR_SHUFFLE()
22732 DAG.MaskedVectorIsZero(N1, DemandedRHS))) { in visitVECTOR_SHUFFLE()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 2793 SDValue DemandedRHS = TLI.SimplifyMultipleUseDemandedBits(RHS, Demanded, DAG); in simplifyMul24() local
2794 if (DemandedLHS || DemandedRHS) in simplifyMul24()
2797 DemandedRHS ? DemandedRHS : RHS); in simplifyMul24()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7584 DemandedRHS.setBit(InnerIdx); in getPackDemandedElts()
36824 APInt DemandedLHS, DemandedRHS; in computeKnownBitsForTargetNode() local
36835 if (!!DemandedRHS) { in computeKnownBitsForTargetNode()
37102 APInt DemandedLHS, DemandedRHS; in ComputeNumSignBitsForTargetNode() local
37104 DemandedRHS); in ComputeNumSignBitsForTargetNode()
37110 if (!!DemandedRHS) in ComputeNumSignBitsForTargetNode()
41204 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedVectorEltsForTargetNode() local
41241 APInt DemandedLHS, DemandedRHS; in SimplifyDemandedVectorEltsForTargetNode() local
41666 if (DemandedLHS || DemandedRHS) { in SimplifyDemandedBitsForTargetNode()
41668 DemandedRHS = DemandedRHS ? DemandedRHS : RHS; in SimplifyDemandedBitsForTargetNode()
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