| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 166 const MachineOperand *DefMO = nullptr; in runOnMachineFunction() local
187 if (DefMO) { in runOnMachineFunction()
191 DefMO = &MO; in runOnMachineFunction()
192 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
193 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
218 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
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| H A D | FixupStatepointCallerSaved.cpp | 485 MachineOperand &DefMO = MI.getOperand(I); in rewriteStatepoint() local
486 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand"); in rewriteStatepoint()
487 Register Reg = DefMO.getReg(); in rewriteStatepoint()
488 assert(DefMO.isTied() && "Def is expected to be tied"); in rewriteStatepoint()
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| H A D | MachineLICM.cpp | 1088 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1089 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1092 Register Reg = DefMO.getReg(); in IsCheapInstruction()
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| H A D | ModuloSchedule.cpp | 1600 for (MachineOperand &DefMO : MI->defs()) { in filterInstructions()
1602 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in filterInstructions()
1611 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in filterInstructions()
1914 for (MachineOperand &DefMO : MI->defs()) { in rewriteUsesOf()
1916 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in rewriteUsesOf()
1925 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in rewriteUsesOf()
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| H A D | MachineInstr.cpp | 1053 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1055 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1057 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1073 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| H A D | RegisterCoalescer.cpp | 1373 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1374 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1383 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1384 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TileShapeInfo.h | 73 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { in deduceImm() local
74 const auto *MI = DefMO.getParent(); in deduceImm()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 199 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
200 if (!DefMO.isReg()) in findStartOfTree()
202 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
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| H A D | WebAssemblyRegStackify.cpp | 645 MachineOperand &DefMO = Def->getOperand(0); in moveAndTeeForMultiUse() local
649 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
651 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 295 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
296 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
297 return &DefMO; in findSingleRegDef()
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| H A D | SIInsertWaitcnts.cpp | 628 MachineOperand &DefMO = Inst.getOperand(I); in updateByEvent() local
629 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
630 TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()
632 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)), in updateByEvent()
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| H A D | SIInstrInfo.h | 820 const MachineOperand &DefMO) const { in isInlineConstant() argument
827 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 448 const MachineOperand &DefMO, unsigned Reg,
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| H A D | ARMBaseInstrInfo.cpp | 4364 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4365 Register Reg = DefMO.getReg(); in getOperandLatency()
4387 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4394 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4422 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4296 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4298 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) { in getOperandLatency()
4299 if (DefMO.isImplicit()) { in getOperandLatency()
4300 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 176 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
177 Register Reg = DefMO.getReg(); in getOperandLatency()
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