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Searched refs:DefMI (Results 1 – 25 of 74) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp96 if (DefMI->getParent() != MBB) in getAccDefMI()
98 if (DefMI->isCopyLike()) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
113 return DefMI; in getAccDefMI()
149 if (DefMI->getParent() != MBB) in hasLoopHazard()
152 if (DefMI->isPHI()) { in hasLoopHazard()
162 } else if (DefMI->isCopyLike()) { in hasLoopHazard()
165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
179 return DefMI == MI; in hasLoopHazard()
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H A DARMHazardRecognizer.cpp28 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
39 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
54 MachineInstr *DefMI = LastMI; in getHazardType() local
67 DefMI = &*I; in getHazardType()
71 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
73 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
H A DARMFixCortexA57AES1742098Pass.cpp367 MachineInstr *DefMI = *It; in analyzeMF() local
371 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
378 MachineBasicBlock::iterator DefIt = DefMI; in analyzeMF()
380 if (DefIt != DefMI->getParent()->end()) { in analyzeMF()
381 LLVM_DEBUG(dbgs() << "Moving Fixup to immediately after " << *DefMI in analyzeMF()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetSchedule.cpp184 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
188 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
197 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
216 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
217 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
241 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
251 return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
302 Register Reg = DefMI->getOperand(DefOperIdx).getReg(); in computeOutputLatency()
303 const MachineFunction &MF = *DefMI->getMF(); in computeOutputLatency()
306 return computeInstrLatency(DefMI); in computeOutputLatency()
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H A DLiveRangeEdit.cpp72 assert(DefMI && "Missing instruction"); in checkRematerializable()
74 if (!TII.isTriviallyReMaterializable(*DefMI)) in checkRematerializable()
90 if (!DefMI) in scanRemattable()
92 checkRematerializable(OrigVNI, DefMI); in scanRemattable()
208 if (DefMI && DefMI != MI) in foldAsLoad()
212 DefMI = MI; in foldAsLoad()
222 if (!DefMI || !UseMI) in foldAsLoad()
227 if (!allUsesAvailableAt(DefMI, LIS.getInstructionIndex(*DefMI), in foldAsLoad()
234 if (!DefMI->isSafeToMove(nullptr, SawStore)) in foldAsLoad()
253 DefMI->addRegisterDead(LI->reg(), nullptr); in foldAsLoad()
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H A DMachineTraceMetrics.cpp628 const MachineInstr *DefMI; member
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
802 if (!Dep.DefMI->isTransient()) in updateDepth()
958 if (!Dep.DefMI->isTransient()) in pushDepHeight()
982 Register Reg = DefMI->getOperand(DefOp).getReg(); in addLiveIns()
1118 addLiveIns(Dep.DefMI, Dep.DefOp, Stack); in computeInstrHeights()
1136 LIR.Height = Heights.lookup(DefMI); in computeInstrHeights()
1189 if (!Dep.DefMI->isTransient()) in getPHIDepth()
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H A DPHIElimination.cpp165 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in runOnMachineFunction() local
166 if (!DefMI) in runOnMachineFunction()
177 MachineBasicBlock *DefMBB = DefMI->getParent(); in runOnMachineFunction()
201 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
202 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
205 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
206 DefMI->eraseFromParent(); in runOnMachineFunction()
496 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
497 if (DefMI->isImplicitDef()) in LowerPHINode()
498 ImpDefs.insert(DefMI); in LowerPHINode()
H A DRegisterCoalescer.cpp855 if (!DefMI) in removeCopyByCommutingDef()
857 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
905 << *DefMI); in removeCopyByCommutingDef()
918 if (NewMI != DefMI) { in removeCopyByCommutingDef()
922 MBB->erase(DefMI); in removeCopyByCommutingDef()
1136 if (!DefMI || !DefMI->isFullCopy()) { in removePartialRedundancy()
1301 if (!DefMI) in reMaterializeTrivialDef()
1303 if (DefMI->isCopyLike()) { in reMaterializeTrivialDef()
2673 assert(DefMI != nullptr); in analyzeValue()
2781 if (DefMI && in analyzeValue()
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H A DMachineCSE.cpp180 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
181 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
183 Register SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
186 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
200 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
204 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
215 DefMI->changeDebugValuesDefReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
217 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp66 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
142 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
148 switch (DefMI.getOpcode()) { in tryToTuneBranch()
194 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
197 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
201 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
249 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
252 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
256 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
275 DefMI.eraseFromParent(); in tryToTuneBranch()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp352 for (auto DefMI : List) { in chooseBestLEA() local
366 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
373 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
383 BestLEA = DefMI; in chooseBestLEA()
527 MachineInstr *DefMI; in removeRedundantAddrCalc() local
540 DefMI->removeFromParent(); in removeRedundantAddrCalc()
541 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
542 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
545 assert(((InstrPos[DefMI] == 1 && in removeRedundantAddrCalc()
547 InstrPos[DefMI] > in removeRedundantAddrCalc()
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H A DX86TileConfig.cpp160 for (auto &DefMI : MRI.def_instructions(R)) { in INITIALIZE_PASS_DEPENDENCY() local
161 MachineBasicBlock &MBB = *DefMI.getParent(); in INITIALIZE_PASS_DEPENDENCY()
162 if (DefMI.isMoveImmediate()) { in INITIALIZE_PASS_DEPENDENCY()
165 assert(Imm == DefMI.getOperand(1).getImm() && in INITIALIZE_PASS_DEPENDENCY()
169 Imm = DefMI.getOperand(1).getImm(); in INITIALIZE_PASS_DEPENDENCY()
182 auto Iter = DefMI.getIterator(); in INITIALIZE_PASS_DEPENDENCY()
H A DX86PreTileConfig.cpp223 MachineInstr *DefMI = MRI->getVRegDef(R); in INITIALIZE_PASS_DEPENDENCY() local
224 assert(DefMI && "R must has one define instruction"); in INITIALIZE_PASS_DEPENDENCY()
225 MachineBasicBlock *DefMBB = DefMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
226 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second) in INITIALIZE_PASS_DEPENDENCY()
228 if (DefMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
229 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2) in INITIALIZE_PASS_DEPENDENCY()
230 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB())) in INITIALIZE_PASS_DEPENDENCY()
231 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def. in INITIALIZE_PASS_DEPENDENCY()
233 WorkList.push_back(DefMI->getOperand(I).getReg()); in INITIALIZE_PASS_DEPENDENCY()
235 RecordShape(DefMI, DefMBB); in INITIALIZE_PASS_DEPENDENCY()
H A DX86CallFrameOptimization.cpp620 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
624 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
625 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
626 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
631 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
635 return &DefMI; in canFoldIntoRegPush()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp280 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
282 assert(DefMI); in isCallViaRegister()
286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
289 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
295 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
296 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
298 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp463 MachineInstr *DefMI; in eliminateTruncSeq() local
490 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
491 if (DefMI) in eliminateTruncSeq()
497 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
499 if (!DefMI) in eliminateTruncSeq()
513 if (DefMI->isPHI()) { in eliminateTruncSeq()
516 for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) { in eliminateTruncSeq()
517 MachineOperand &opnd = DefMI->getOperand(i); in eliminateTruncSeq()
533 } else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) { in eliminateTruncSeq()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp442 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() local
446 unsigned Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
448 Register SrcReg = DefMI->getOperand(1).getReg(); in getDefSrcRegIgnoringCopies()
452 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
454 Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
476 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
635 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() local
636 if (!DefMI) in isKnownNeverNaN()
650 for (const auto &Op : DefMI->uses()) in isKnownNeverNaN()
656 switch (DefMI->getOpcode()) { in isKnownNeverNaN()
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp533 if (!DefMI) in simplifyCode()
536 unsigned DefOpc = DefMI->getOpcode(); in simplifyCode()
615 .add(DefMI->getOperand(1)); in simplifyCode()
651 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
652 if (!DefMI) in simplifyCode()
654 unsigned DefOpcode = DefMI->getOpcode(); in simplifyCode()
696 LLVM_DEBUG(DefMI->dump()); in simplifyCode()
697 ToErase = DefMI; in simplifyCode()
715 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() local
719 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
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H A DPPCInstrInfo.h209 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
213 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
219 MachineInstr &DefMI) const;
223 unsigned ConstantOpNo, MachineInstr &DefMI,
238 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
243 const MachineInstr &DefMI,
248 const MachineInstr &DefMI,
414 const MachineInstr &DefMI, unsigned DefIdx,
425 const MachineInstr &DefMI, in hasLowDefLatency() argument
571 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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H A DPPCVSXSwapRemoval.cpp620 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
621 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
623 int DefIdx = SwapMap[DefMI]; in formWebs()
631 LLVM_DEBUG(DefMI->dump()); in formWebs()
725 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
726 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
727 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
737 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
756 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
803 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval()
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H A DPPCInstrInfo.cpp173 if (!DefMI.getParent()) in getOperandLatency()
3299 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 || in getForwardingDefMI()
3307 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3344 if (DefMI) { in getForwardingDefMI()
3356 return DefMI; in getForwardingDefMI()
3717 if (!DefMI) in convertToImmediateForm()
3724 *KilledDef = DefMI; in convertToImmediateForm()
4446 if ((&*It) == &DefMI) in isRegElgibleForForwarding()
4514 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4815 LLVM_DEBUG(DefMI.dump()); in transformToNewImmFormFedByAdd()
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/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp496 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
497 bool Invert = !DefMI; in optimizeSelect()
498 if (!DefMI) in optimizeSelect()
499 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
500 if (!DefMI) in optimizeSelect()
512 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
515 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
518 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
536 SeenMIs.erase(DefMI); in optimizeSelect()
542 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/llvm-project-15.0.7/llvm/unittests/Target/AMDGPU/
H A DExecMayBeModifiedBeforeAnyUse.cpp55 MachineInstr *DefMI = in TEST() local
72 ASSERT_FALSE(execMayBeModifiedBeforeAnyUse(MRI, R, *DefMI)); in TEST()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h173 unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
197 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp576 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
582 switch (DefMI.getOpcode()) { in FoldImmediate()
588 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
590 assert(DefMI.getOperand(1).isImm()); in FoldImmediate()
591 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
593 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); in FoldImmediate()
599 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
601 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
602 if (!DefMI.getOperand(3).isImm()) in FoldImmediate()
605 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); in FoldImmediate()
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