184   const MachineInstr *DefMI, unsigned DefOperIdx,  in computeOperandLatency()  argument
188     return TII->defaultDefLatency(SchedModel, *DefMI);  in computeOperandLatency()
193       OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,  in computeOperandLatency()
197       unsigned DefClass = DefMI->getDesc().getSchedClass();  in computeOperandLatency()
204     unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);  in computeOperandLatency()
212         std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));  in computeOperandLatency()
216   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);  in computeOperandLatency()
217   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);  in computeOperandLatency()
240   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()  in computeOperandLatency()
241       && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()  in computeOperandLatency()
244            << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";  in computeOperandLatency()
251   return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);  in computeOperandLatency()
289 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,  in computeOutputLatency()  argument
302   Register Reg = DefMI->getOperand(DefOperIdx).getReg();  in computeOutputLatency()
303   const MachineFunction &MF = *DefMI->getMF();  in computeOutputLatency()
306     return computeInstrLatency(DefMI);  in computeOutputLatency()
311     const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);  in computeOutputLatency()