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Searched refs:CTTZ (Results 1 – 25 of 46) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/AMDGPU/
H A Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dffs-1.ll151 ; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
152 ; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
167 ; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0
168 ; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1
183 ; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true), !range !1
184 ; TARGET-NEXT: [[TMP1:%.*]] = trunc i64 [[CTTZ]] to i32
H A Dintrinsics.ll343 ; CHECK-NEXT: [[CTTZ:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[OR]], i1 true), !range [[RNG3:![…
344 ; CHECK-NEXT: ret i32 [[CTTZ]]
354 ; CHECK-NEXT: [[CTTZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true)
355 ; CHECK-NEXT: ret <2 x i32> [[CTTZ]]
386 ; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[VALUE:%.*]], i1 false), !range [[RNG4…
387 ; CHECK-NEXT: ret i32 [[CTTZ]]
397 ; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false)
398 ; CHECK-NEXT: ret <2 x i32> [[CTTZ]]
H A Dadd2.ll332 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !0
333 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -8
354 ; CHECK-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[A:%.*]], i1 true), !range !1
355 ; CHECK-NEXT: [[B:%.*]] = or i16 [[CTTZ]], -16
H A Dand.ll1773 ; CTTZ(ShlC) < LShrC
1875 ; LShrC < CTTZ(ShlC) < LShrC + CTTZ(AndC)
1902 ; CTTZ(ShlC) > LShrC + CTTZ(AndC)
1914 ; LShrC + CTTZ(AndC) > BitWidth
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/X86/
H A Dcttz.ll5 ; Recognize CTTZ builtin pattern.
67 ; Recognize CTTZ builtin pattern.
116 ; Recognize CTTZ builtin pattern.
179 ; Recognize CTTZ builtin pattern.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2914 { ISD::CTTZ, MVT::v8i64, 10 }, in getTypeBasedIntrinsicInstrCost()
2915 { ISD::CTTZ, MVT::v16i32, 14 }, in getTypeBasedIntrinsicInstrCost()
2916 { ISD::CTTZ, MVT::v32i16, 12 }, in getTypeBasedIntrinsicInstrCost()
2917 { ISD::CTTZ, MVT::v64i8, 9 }, in getTypeBasedIntrinsicInstrCost()
2957 { ISD::CTTZ, MVT::v8i64, 20 }, in getTypeBasedIntrinsicInstrCost()
2958 { ISD::CTTZ, MVT::v16i32, 28 }, in getTypeBasedIntrinsicInstrCost()
2959 { ISD::CTTZ, MVT::v32i16, 24 }, in getTypeBasedIntrinsicInstrCost()
2960 { ISD::CTTZ, MVT::v64i8, 18 }, in getTypeBasedIntrinsicInstrCost()
3056 { ISD::CTTZ, MVT::v2i64, 4 }, in getTypeBasedIntrinsicInstrCost()
3205 { ISD::CTTZ, MVT::v16i8, 9 } in getTypeBasedIntrinsicInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp150 case ARC::CTTZ: in runOnMachineFunction()
H A DARCISelLowering.cpp172 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in ARCTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h701 CTTZ, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-bit-counting-pred.ll82 ; CTTZ
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp189 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
261 setOperationAction(ISD::CTTZ, T, Custom); in initializeHVXLowering()
2412 case ISD::CTTZ: in LowerHvxOperation()
2455 case ISD::CTTZ: return LowerHvxCttz(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1561 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1562 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1632 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp104 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
105 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp345 case ISD::CTTZ: in LegalizeOp()
792 case ISD::CTTZ: in Expand()
H A DSelectionDAGDumper.cpp433 case ISD::CTTZ: return "cttz"; in getOperationName()
H A DLegalizeDAG.cpp2711 case ISD::CTTZ: in ExpandNode()
4469 case ISD::CTTZ: in PromoteNode()
4475 if (Node->getOpcode() == ISD::CTTZ || in PromoteNode()
4481 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1642 setOperationAction(ISD::CTTZ, VT, Custom); in addTypeForFixedLengthSVE()
5609 case ISD::CTTZ: in LowerOperation()
18251 SDValue Zero, CTTZ; in foldCSELofCTTZ() local
18255 CTTZ = N->getOperand(1); in foldCSELofCTTZ()
18258 CTTZ = N->getOperand(0); in foldCSELofCTTZ()
18262 if ((CTTZ.getOpcode() != ISD::CTTZ && CTTZ.getOpcode() != ISD::TRUNCATE) || in foldCSELofCTTZ()
18263 (CTTZ.getOpcode() == ISD::TRUNCATE && in foldCSELofCTTZ()
18264 CTTZ.getOperand(0).getOpcode() != ISD::CTTZ)) in foldCSELofCTTZ()
18267 assert((CTTZ.getValueType() == MVT::i32 || CTTZ.getValueType() == MVT::i64) && in foldCSELofCTTZ()
18275 : CTTZ.getOperand(0); in foldCSELofCTTZ()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp230 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand); in WebAssemblyTargetLowering()
233 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
1440 case ISD::CTTZ: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp128 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp343 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
368 {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, in AMDGPUTargetLowering()
386 ISD::CTTZ, ISD::CTLZ, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
1174 case ISD::CTTZ: in LowerOperation()
2236 return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF; in isCttzOpc()
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp535 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in NVPTXTargetLowering()
536 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in NVPTXTargetLowering()
537 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in NVPTXTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp62 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp128 setOperationAction(ISD::CTTZ, MVT::i32, Legal); in LanaiTargetLowering()
/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DLegalizerHelperTest.cpp296 auto CTTZ = in TEST_F() local
303 Helper.narrowScalar(*CTTZ, 1, LLT::scalar(32))); in TEST_F()

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