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Searched refs:CTPOP (Results 1 – 25 of 45) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-ctpop.mir16 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:sgpr(s32) = G_CTPOP [[COPY]](s32)
17 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTPOP]](s32)
34 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:vgpr(s32) = G_CTPOP [[COPY]](s32)
35 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTPOP]](s32)
53 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:sgpr(s32) = G_CTPOP [[COPY]](s64)
54 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTPOP]](s32)
73 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:vgpr(s32) = G_CTPOP [[UV]](s32)
75 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[CTPOP1]], [[CTPOP]]
H A Dlegalize-ctpop.mir15 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
16 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
37 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
38 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
58 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
59 ; CHECK-NEXT: $vgpr0 = COPY [[CTPOP]](s32)
75 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s64)
76 ; CHECK-NEXT: $vgpr0 = COPY [[CTPOP]](s32)
93 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
133 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-ctpop.mir51 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
71 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
92 ; CHECK: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
120 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
147 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
174 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
200 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
224 ; CHECK: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
245 ; CHECK: [[CTPOP:%[0-9]+]]:_(<16 x s8>) = G_CTPOP [[BITCAST]](<16 x s8>)
290 ; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
[all …]
H A Dlegalize-cttz.mir109 ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<4 x s32>) = G_CTPOP [[AND]](<4 x s32>)
110 ; CHECK-NEXT: $q0 = COPY [[CTPOP]](<4 x s32>)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2867 { ISD::CTPOP, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2868 { ISD::CTPOP, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2869 { ISD::CTPOP, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2870 { ISD::CTPOP, MVT::v32i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2871 { ISD::CTPOP, MVT::v8i16, 1 }, in getTypeBasedIntrinsicInstrCost()
2872 { ISD::CTPOP, MVT::v16i8, 1 }, in getTypeBasedIntrinsicInstrCost()
2875 { ISD::CTPOP, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2876 { ISD::CTPOP, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()
2877 { ISD::CTPOP, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()
2878 { ISD::CTPOP, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h703 CTPOP, enumerator
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp387 {ISD::CTPOP, MVT::v2i64, 4}, in getIntrinsicInstrCost()
388 {ISD::CTPOP, MVT::v4i32, 3}, in getIntrinsicInstrCost()
389 {ISD::CTPOP, MVT::v8i16, 2}, in getIntrinsicInstrCost()
390 {ISD::CTPOP, MVT::v16i8, 1}, in getIntrinsicInstrCost()
391 {ISD::CTPOP, MVT::i64, 4}, in getIntrinsicInstrCost()
392 {ISD::CTPOP, MVT::v2i32, 3}, in getIntrinsicInstrCost()
393 {ISD::CTPOP, MVT::v4i16, 2}, in getIntrinsicInstrCost()
394 {ISD::CTPOP, MVT::v8i8, 1}, in getIntrinsicInstrCost()
395 {ISD::CTPOP, MVT::i32, 5}, in getIntrinsicInstrCost()
399 if (const auto *Entry = CostTableLookup(CtpopCostTbl, ISD::CTPOP, MTy)) { in getIntrinsicInstrCost()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-bit-counting-pred.ll5 ; CTPOP
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1246 auto CTPOP = MIRBuilder.buildCTPOP(VTy, Val); in legalizeCTPOP() local
1249 Register HSum = CTPOP.getReg(0); in legalizeCTPOP()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp2148 case ISD::CTPOP: { in SimplifyDemandedBits()
3960 SDValue CTPOP = N0; in simplifySetCCWithCTPOP() local
3963 CTPOP = N0.getOperand(0); in simplifySetCCWithCTPOP()
3965 if (CTPOP.getOpcode() != ISD::CTPOP || !CTPOP.hasOneUse()) in simplifySetCCWithCTPOP()
3968 EVT CTVT = CTPOP.getValueType(); in simplifySetCCWithCTPOP()
3969 SDValue CTOp = CTPOP.getOperand(0); in simplifySetCCWithCTPOP()
3973 if (VT.isVector() && TLI.isOperationLegal(ISD::CTPOP, CTVT)) in simplifySetCCWithCTPOP()
7948 (!isOperationLegalOrCustom(ISD::CTPOP, VT) && in expandCTLZ()
7969 return DAG.getNode(ISD::CTPOP, dl, VT, Op); in expandCTLZ()
7997 (!isOperationLegalOrCustom(ISD::CTPOP, VT) && in expandCTTZ()
[all …]
H A DLegalizeVectorOps.cpp348 case ISD::CTPOP: in LegalizeOp()
779 case ISD::CTPOP: in Expand()
H A DSelectionDAGDumper.cpp432 case ISD::CTPOP: return "ctpop"; in getOperationName()
H A DLegalizeIntegerTypes.cpp69 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break; in PromoteIntegerResult()
587 if (N->getOpcode() == ISD::CTPOP && !OVT.isVector() && TLI.isTypeLegal(NVT) && in PromoteIntRes_CTPOP_PARITY()
588 !TLI.isOperationLegalOrCustomOrPromote(ISD::CTPOP, NVT)) { in PromoteIntRes_CTPOP_PARITY()
613 !TLI.isOperationLegal(ISD::CTPOP, NVT) && in PromoteIntRes_CTTZ()
2420 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; in ExpandIntegerResult()
3342 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), in ExpandIntRes_CTPOP()
3343 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); in ExpandIntRes_CTPOP()
H A DLegalizeDAG.cpp2677 if (TLI.isOperationLegalOrPromote(ISD::CTPOP, VT)) { in ExpandPARITY()
2678 Result = DAG.getNode(ISD::CTPOP, dl, VT, Op); in ExpandPARITY()
2702 case ISD::CTPOP: in ExpandNode()
4473 case ISD::CTPOP: in PromoteNode()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1565 setOperationAction(ISD::CTPOP, MVT::i8, Promote); in HexagonTargetLowering()
1566 setOperationAction(ISD::CTPOP, MVT::i16, Promote); in HexagonTargetLowering()
1567 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in HexagonTargetLowering()
1568 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1632 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, in HexagonTargetLowering()
H A DHexagonISelLoweringHVX.cpp172 setOperationAction(ISD::CTPOP, T, Legal); in initializeHVXLowering()
262 setOperationAction(ISD::CTPOP, T, Custom); in initializeHVXLowering()
2410 case ISD::CTPOP: in LowerHvxOperation()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp108 setOperationAction(ISD::CTPOP, MVT::i8, Expand); in MSP430TargetLowering()
109 setOperationAction(ISD::CTPOP, MVT::i16, Expand); in MSP430TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp228 setOperationAction(ISD::CTPOP, MVT::v16i8, Legal); in WebAssemblyTargetLowering()
233 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}) in WebAssemblyTargetLowering()
1438 case ISD::CTPOP: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp115 setOperationAction(ISD::CTPOP, VT, Expand); in BPFTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp166 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in R600TargetLowering()
169 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in R600TargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp202 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
204 setOperationAction(ISD::CTPOP, VT, Expand); in SystemZTargetLowering()
283 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in SystemZTargetLowering()
284 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in SystemZTargetLowering()
374 setOperationAction(ISD::CTPOP, VT, Legal); in SystemZTargetLowering()
376 setOperationAction(ISD::CTPOP, VT, Custom); in SystemZTargetLowering()
5747 case ISD::CTPOP: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp400 setOperationAction(ISD::CTPOP, MVT::i32, Legal); in MipsTargetLowering()
401 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in MipsTargetLowering()
403 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in MipsTargetLowering()
404 setOperationAction(ISD::CTPOP, MVT::i64, Expand); in MipsTargetLowering()
/llvm-project-15.0.7/llvm/docs/
H A DWritingAnLLVMBackend.rst1463 is rarely used. In ``SparcISelLowering.cpp``, the action for ``CTPOP`` (an
1470 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1473 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp63 setOperationAction(ISD::CTPOP, MVT::i32, Expand); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp126 setOperationAction(ISD::CTPOP, MVT::i32, Legal); in LanaiTargetLowering()

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