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Searched refs:BaseReg (Results 1 – 25 of 90) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp517 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optLEAALU()
521 if (BaseReg == IndexReg) in optLEAALU()
523 std::swap(BaseReg, IndexReg); in optLEAALU()
526 if (BaseReg == IndexReg) in optLEAALU()
582 if (BaseReg != 0) in optTwoAddrLEA()
583 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in optTwoAddrLEA()
596 if (DestReg != BaseReg) in optTwoAddrLEA()
627 .addReg(BaseReg); in optTwoAddrLEA()
770 if (BaseReg != 0) in processInstrForSlow3OpLEA()
771 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit); in processInstrForSlow3OpLEA()
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H A DX86InsertPrefetch.cpp83 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
85 return (BaseReg == 0 || in IsMemOpCompatibleWithPrefetch()
86 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) || in IsMemOpCompatibleWithPrefetch()
87 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) && in IsMemOpCompatibleWithPrefetch()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp46 unsigned BaseReg = FrameReg; in replaceFrameIndex() local
51 .addReg(BaseReg) in replaceFrameIndex()
60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
61 if (!BaseReg) { in replaceFrameIndex()
66 BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj); in replaceFrameIndex()
67 assert(BaseReg && "Register scavenging failed."); in replaceFrameIndex()
68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex()
72 RS->setRegUsed(BaseReg); in replaceFrameIndex()
76 .addReg(BaseReg, RegState::Define) in replaceFrameIndex()
94 .addReg(BaseReg, KillState) in replaceFrameIndex()
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H A DARCOptAddrMode.cpp101 MachineOperand &Incr, unsigned BaseReg);
105 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
298 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
308 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) { in canJoinInstructions()
316 for (MachineInstr &MI : MRI->use_nodbg_instructions(BaseReg)) { in canJoinInstructions()
354 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
460 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
474 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp131 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
143 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
219 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
231 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
237 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
240 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
254 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
314 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
320 BaseReg = DestReg; in emitThumbRegPlusImmediate()
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H A DThumb2InstrInfo.cpp294 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
296 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
306 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
328 .addReg(BaseReg) in emitT2RegPlusImmediate()
340 .addReg(BaseReg) in emitT2RegPlusImmediate()
353 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
356 .addReg(BaseReg) in emitT2RegPlusImmediate()
359 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
363 assert((DestReg != ARM::SP || BaseReg == ARM::SP) && in emitT2RegPlusImmediate()
371 .addReg(BaseReg) in emitT2RegPlusImmediate()
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H A DARMBaseRegisterInfo.cpp681 Register BaseReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in materializeFrameBaseRegister() local
682 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
684 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
690 return BaseReg; in materializeFrameBaseRegister()
693 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
712 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
715 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); in resolveFrameIndex()
722 Register BaseReg, in isFrameOffsetLegal() argument
765 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
H A DThumb2SizeReduction.cpp500 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
501 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
507 if (MO.getReg() == BaseReg) { in ReduceLoadStore()
530 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
532 if (MO.getReg() == BaseReg) in ReduceLoadStore()
538 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
539 if (BaseReg != ARM::SP) in ReduceLoadStore()
551 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
552 if (BaseReg == ARM::SP && in ReduceLoadStore()
557 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLocalStackSlotAllocation.cpp272 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
281 return TRI->isFrameOffsetLegal(&MI, BaseReg, Offset); in lookupCandidateBaseReg()
346 Register BaseReg; in insertFrameReferenceRegisters() local
390 lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
392 LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
409 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
419 BaseReg = TRI->materializeFrameBaseRegister(Entry, FrameIdx, InstrOffset); in insertFrameReferenceRegisters()
423 << " into " << printReg(BaseReg, TRI) << '\n'); in insertFrameReferenceRegisters()
433 assert(BaseReg && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
437 TRI->resolveFrameIndex(MI, BaseReg, Offset); in insertFrameReferenceRegisters()
H A DImplicitNullChecks.cpp380 const Register BaseReg = AddrMode.BaseReg, ScaledReg = AddrMode.ScaledReg; in isSuitableMemoryOp() local
385 if (BaseReg != PointerReg && ScaledReg != PointerReg) in isSuitableMemoryOp()
391 if ((BaseReg && in isSuitableMemoryOp()
392 TRI->getRegSizeInBits(BaseReg, MRI) != PointerRegSizeInBits) || in isSuitableMemoryOp()
451 if (CalculateDisplacementFromAddrMode(BaseReg, 1)) in isSuitableMemoryOp()
461 if ((BaseReg && BaseReg != PointerReg && !BaseRegIsConstVal) || in isSuitableMemoryOp()
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp85 if (!mi_match(Ptr, MRI, m_GPtrAdd(m_Reg(Info.BaseReg), m_Reg(PtrAddRHS)))) { in getPointerInfo()
86 Info.BaseReg = Ptr; in getPointerInfo()
115 if (!BasePtr0.BaseReg.isValid() || !BasePtr1.BaseReg.isValid()) in aliasIsKnownForLoadStore()
122 if (BasePtr0.BaseReg == BasePtr1.BaseReg) { in aliasIsKnownForLoadStore()
152 auto *Base0Def = getDefIgnoringCopies(BasePtr0.BaseReg, MRI); in aliasIsKnownForLoadStore()
153 auto *Base1Def = getDefIgnoringCopies(BasePtr1.BaseReg, MRI); in aliasIsKnownForLoadStore()
204 Register BaseReg; in instMayAlias() local
208 m_GPtrAdd(m_Reg(BaseReg), m_ICst(Offset)))) { in instMayAlias()
209 BaseReg = LS->getPointerReg(); in instMayAlias()
215 return {LS->isVolatile(), LS->isAtomic(), BaseReg, in instMayAlias()
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/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelDAGToDAG.cpp66 SDValue BaseReg; member
144 BaseReg = Reg; in setBaseReg()
154 if (BaseReg.getNode()) in dump()
155 BaseReg.getNode()->dump(); in dump()
413 AM.BaseReg = N; in matchAddressBase()
488 AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) { in matchAddressRecursively()
537 AM.BaseReg = N.getOperand(0); in matchADD()
721 Base = AM.BaseReg; in SelectARID()
768 Index = AM.BaseReg; in SelectARII()
770 Base = AM.BaseReg; in SelectARII()
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/llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1298 if (BaseReg != 0 && in CheckBaseRegAndIndexRegAndScale()
1299 !(BaseReg == X86::RIP || BaseReg == X86::EIP || in CheckBaseRegAndIndexRegAndScale()
1329 (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP && in CheckBaseRegAndIndexRegAndScale()
1330 BaseReg != X86::SI && BaseReg != X86::DI))) { in CheckBaseRegAndIndexRegAndScale()
1362 if ((BaseReg != X86::BX && BaseReg != X86::BP) || in CheckBaseRegAndIndexRegAndScale()
1372 (BaseReg == X86::RIP || BaseReg == X86::EIP)) { in CheckBaseRegAndIndexRegAndScale()
1786 BaseReg = BaseReg ? BaseReg : 1; in CreateMemForMSInlineAsm()
2589 BaseReg = 0; in parseIntelOperand()
2594 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in parseIntelOperand()
2620 if ((BaseReg == X86::SI || BaseReg == X86::DI) && in parseIntelOperand()
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H A DX86Operand.h65 unsigned BaseReg; member
145 if (Mem.BaseReg) in print()
146 OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg); in print()
195 return Mem.BaseReg; in getMemBaseReg()
335 return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP; in isSibMem()
689 Res->Mem.BaseReg = 0;
707 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
715 assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
724 Res->Mem.BaseReg = BaseReg;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
157 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
166 PrevBaseReg = BaseReg; in runOnMachineFunction()
H A DAArch64FalkorHWPFFix.cpp217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
647 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP) in getLoadInfo()
652 LI.BaseReg = BaseReg; in getLoadInfo()
662 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
756 NewLdI.BaseReg = ScratchReg; in runOnLoop()
773 .addReg(LdI.BaseReg) in runOnLoop()
786 TII->get(AArch64::ORRXrs), LdI.BaseReg) in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp1268 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingStore()
1589 if (BaseReg == MIBaseReg) { in findMatchingInsn()
1741 if (!ModifiedRegUnits.available(BaseReg)) in findMatchingInsn()
1870 if (MI.getOperand(0).getReg() != BaseReg || in isMatchingUpdateInsn()
1871 MI.getOperand(1).getReg() != BaseReg) in isMatchingUpdateInsn()
1930 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
1972 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnForward()
1973 !UsedRegUnits.available(BaseReg) || in findMatchingUpdateInsnForward()
2001 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward()
2047 if (!ModifiedRegUnits.available(BaseReg) || in findMatchingUpdateInsnBackward()
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H A DAArch64RegisterInfo.h106 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
110 void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
H A DAArch64RegisterInfo.cpp600 Register BaseReg, in isFrameOffsetLegal() argument
622 Register BaseReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass); in materializeFrameBaseRegister() local
623 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
626 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
631 return BaseReg; in materializeFrameBaseRegister()
634 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex() argument
648 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp131 unsigned BaseReg; member
173 return Mem.BaseReg; in getMemBaseReg()
616 Op->Mem.BaseReg = 0; in MorphToMemImm()
624 MorphToMemRegReg(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegReg()
628 Op->Mem.BaseReg = BaseReg; in MorphToMemRegReg()
636 MorphToMemRegImm(unsigned BaseReg, std::unique_ptr<LanaiOperand> Op, in MorphToMemRegImm()
640 Op->Mem.BaseReg = BaseReg; in MorphToMemRegImm()
909 unsigned BaseReg = 0; in parseMemoryOperand() local
966 BaseReg = Op->getReg(); in parseMemoryOperand()
994 if (!BaseReg || Lexer.isNot(AsmToken::RBrac)) { in parseMemoryOperand()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp26 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
75 SDValue &BaseReg, in SelectGlobalValueVariableOffset() argument
78 BaseReg = Addr; in SelectGlobalValueVariableOffset()
/llvm-project-15.0.7/llvm/include/llvm/MC/MCParser/
H A DMCTargetAsmParser.h67 StringRef BaseReg; member
73 : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()), in IntelExpr()
78 : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg), in IntelExpr()
83 bool hasBaseReg() const { return !BaseReg.empty(); } in hasBaseReg()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h49 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
52 if (Op.isReg() && Op.getReg() == BaseReg) in isLDMBaseRegInList()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp273 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
280 setMemOp(IT, 1, MCOperand::createReg(BaseReg)); in generateLEATemplatesCommon()
289 RestrictDestRegs(BaseReg, IndexReg, PossibleDestRegsNow); in generateLEATemplatesCommon()
299 CT.Config = formatv("{3}(%{0}, %{1}, {2})", RegInfo.getName(BaseReg), in generateLEATemplatesCommon()
337 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
342 State.getRATC().getRegister(BaseReg).aliasedBits(); in generateCodeTemplates()
397 [this](unsigned BaseReg, unsigned IndexReg, in generateCodeTemplates()
401 State.getRATC().getRegister(BaseReg).aliasedBits()); in generateCodeTemplates()
/llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp1286 unsigned BaseReg = 0; in parseMEMOperand() local
1287 if (ParseRegister(BaseReg, S, E)) in parseMEMOperand()
1296 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset)) in parseMEMOperand()
1297 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset))); in parseMEMOperand()
1316 unsigned BaseReg = VE::NoRegister; in parseMEMAsOperand() local
1335 if (ParseRegister(BaseReg, S, E)) in parseMEMAsOperand()
1354 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1360 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
1368 if (ParseRegister(BaseReg, S, E)) in parseMEMAsOperand()
1374 if (ParseRegister(BaseReg, S, E)) in parseMEMAsOperand()
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