427     unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0;  member in __anonad53f99c0111::X86AsmParser::IntelExprStateMachine
459     unsigned getBaseReg() const { return BaseReg; }  in getBaseReg()
675           if (!BaseReg) {  in onPlus()
676             BaseReg = TmpReg;  in onPlus()
734           if (!BaseReg) {  in onMinus()
735             BaseReg = TmpReg;  in onMinus()
978           if (!BaseReg) {  in onRBrac()
979             BaseReg = TmpReg;  in onRBrac()
1139                                unsigned BaseReg, unsigned IndexReg,
1291 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,  in CheckBaseRegAndIndexRegAndScale()  argument
1298   if (BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1299       !(BaseReg == X86::RIP || BaseReg == X86::EIP ||  in CheckBaseRegAndIndexRegAndScale()
1300         X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1301         X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) ||  in CheckBaseRegAndIndexRegAndScale()
1302         X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg))) {  in CheckBaseRegAndIndexRegAndScale()
1319   if (((BaseReg == X86::RIP || BaseReg == X86::EIP) && IndexReg != 0) ||  in CheckBaseRegAndIndexRegAndScale()
1328   if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1329       (Is64BitMode || (BaseReg != X86::BX && BaseReg != X86::BP &&  in CheckBaseRegAndIndexRegAndScale()
1330                        BaseReg != X86::SI && BaseReg != X86::DI))) {  in CheckBaseRegAndIndexRegAndScale()
1335   if (BaseReg == 0 &&  in CheckBaseRegAndIndexRegAndScale()
1341   if (BaseReg != 0 && IndexReg != 0) {  in CheckBaseRegAndIndexRegAndScale()
1342     if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1349     if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&  in CheckBaseRegAndIndexRegAndScale()
1356     if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {  in CheckBaseRegAndIndexRegAndScale()
1362       if ((BaseReg != X86::BX && BaseReg != X86::BP) ||  in CheckBaseRegAndIndexRegAndScale()
1371   if (!Is64BitMode && BaseReg != 0 &&  in CheckBaseRegAndIndexRegAndScale()
1372       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {  in CheckBaseRegAndIndexRegAndScale()
1680         unsigned OrigReg = OrigOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1681         unsigned FinalReg = FinalOp.Mem.BaseReg;  in VerifyAndAdjustOperands()
1715         FinalOp.Mem.BaseReg = FinalReg;  in VerifyAndAdjustOperands()
1744     unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,  in CreateMemForMSInlineAsm()  argument
1777   if (IsGlobalLV && (BaseReg || IndexReg)) {  in CreateMemForMSInlineAsm()
1780                                              BaseReg && IndexReg));  in CreateMemForMSInlineAsm()
1786   BaseReg = BaseReg ? BaseReg : 1;  in CreateMemForMSInlineAsm()
1788       getPointerWidth(), SegReg, Disp, BaseReg, IndexReg, Scale, Start, End,  in CreateMemForMSInlineAsm()
2586   unsigned BaseReg = SM.getBaseReg();  in parseIntelOperand()  local
2588   if (IndexReg && BaseReg == X86::RIP)  in parseIntelOperand()
2589     BaseReg = 0;  in parseIntelOperand()
2594   if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&  in parseIntelOperand()
2596     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2604       (X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2605        X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||  in parseIntelOperand()
2606        X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))  in parseIntelOperand()
2607     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2620   if ((BaseReg == X86::SI || BaseReg == X86::DI) &&  in parseIntelOperand()
2622     std::swap(BaseReg, IndexReg);  in parseIntelOperand()
2624   if ((BaseReg || IndexReg) &&  in parseIntelOperand()
2625       CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in parseIntelOperand()
2629     return CreateMemForMSInlineAsm(RegNo, Disp, BaseReg, IndexReg, Scale, Start,  in parseIntelOperand()
2649       } else if (!BaseReg && !IndexReg && Disp &&  in parseIntelOperand()
2664   if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister))  in parseIntelOperand()
2666         getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End,  in parseIntelOperand()
2967   unsigned BaseReg = 0, IndexReg = 0, Scale = 1;  in ParseMemOperand()  local
2979     BaseReg = cast<X86MCExpr>(E)->getRegNo();  in ParseMemOperand()
2980     if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)  in ParseMemOperand()
3008         if (BaseReg == X86::RIP)  in ParseMemOperand()
3026             if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&  in ParseMemOperand()
3044   if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&  in ParseMemOperand()
3051   if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),  in ParseMemOperand()
3055   if (SegReg || BaseReg || IndexReg)  in ParseMemOperand()
3057                                              BaseReg, IndexReg, Scale, StartLoc,  in ParseMemOperand()