462   Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();  in checkRegUsage()  local
475       if (TRI->regsOverlap(Reg, BaseReg)) {  in checkRegUsage()
514   Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();  in optLEAALU()  local
517     BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optLEAALU()
521     if (BaseReg == IndexReg)  in optLEAALU()
523     std::swap(BaseReg, IndexReg);  in optLEAALU()
526   if (BaseReg == IndexReg)  in optLEAALU()
535                .addReg(BaseReg, KilledBase ? RegState::Kill : 0);  in optLEAALU()
573   Register BaseReg = Base.getReg();  in optTwoAddrLEA()  local
582     if (BaseReg != 0)  in optTwoAddrLEA()
583       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optTwoAddrLEA()
593   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&  in optTwoAddrLEA()
594       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
596     if (DestReg != BaseReg)  in optTwoAddrLEA()
597       std::swap(BaseReg, IndexReg);  in optTwoAddrLEA()
602         .addReg(BaseReg).addReg(IndexReg)  in optTwoAddrLEA()
607         .addReg(BaseReg).addReg(IndexReg);  in optTwoAddrLEA()
609   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
624           .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);  in optTwoAddrLEA()
627           .addReg(BaseReg);  in optTwoAddrLEA()
634           .addReg(BaseReg).addImm(Disp.getImm())  in optTwoAddrLEA()
638           .addReg(BaseReg).addImm(Disp.getImm());  in optTwoAddrLEA()
641   } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {  in optTwoAddrLEA()
766   Register BaseReg = Base.getReg();  in processInstrForSlow3OpLEA()  local
770     if (BaseReg != 0)  in processInstrForSlow3OpLEA()
771       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in processInstrForSlow3OpLEA()
777   bool IsInefficientBase = isInefficientLEAReg(BaseReg);  in processInstrForSlow3OpLEA()
782   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
794   if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {  in processInstrForSlow3OpLEA()
796     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
797       std::swap(BaseReg, IndexReg);  in processInstrForSlow3OpLEA()
802                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
808                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
854   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
863     bool BIK = Base.isKill() && BaseReg != IndexReg;  in processInstrForSlow3OpLEA()
864     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()