Home
last modified time | relevance | path

Searched refs:ArgReg (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3307 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall() local
3320 ArgVT, ArgReg); in fastLowerCall()
3332 ArgReg = fastEmitZExtFromI1(MVT::i8, ArgReg); in fastLowerCall()
3335 if (ArgReg == 0) in fastLowerCall()
3340 ArgVT, ArgReg); in fastLowerCall()
3349 ArgVT, ArgReg); in fastLowerCall()
3352 ArgVT, ArgReg); in fastLowerCall()
3355 ArgVT, ArgReg); in fastLowerCall()
3362 ArgReg = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg); in fastLowerCall()
3363 assert(ArgReg && "Failed to emit a bitcast!"); in fastLowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1193 Register ArgReg = getRegForValue(ArgVal); in processCallArgs() local
1194 if (!ArgReg) in processCallArgs()
1205 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1206 if (!ArgReg) in processCallArgs()
1213 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1214 if (!ArgReg) in processCallArgs()
1225 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
H A DMipsISelLowering.cpp3684 Register ArgReg = VA.getLocReg(); in LowerFormalArguments() local
3689 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); in LowerFormalArguments()
4387 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs() local
4388 unsigned VReg = addLiveIn(MF, ArgReg, RC); in copyByValRegs()
4427 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
4428 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); in passByValArg()
4476 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg() local
4477 RegsToPass.push_back(std::make_pair(ArgReg, Val)); in passByValArg()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h463 static void mapping(IO &YamlIO, CallSiteInfo::ArgRegPair &ArgReg) {
464 YamlIO.mapRequired("arg", ArgReg.ArgNo);
465 YamlIO.mapRequired("reg", ArgReg.Reg);
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp709 Register ArgReg = Args[i].Regs[Part]; in handleAssignments() local
778 Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA); in handleAssignments()
783 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
786 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); in handleAssignments()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp1147 for (std::pair<MCRegister, Register> ArgReg : ImplicitArgRegs) { in handleImplicitCallArguments()
1148 MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second); in handleImplicitCallArguments()
1149 CallInst.addReg(ArgReg.first, RegState::Implicit); in handleImplicitCallArguments()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMIRPrinter.cpp524 for (auto ArgReg : CSInfo.second) { in convertCallSiteObjects() local
526 YmlArgReg.ArgNo = ArgReg.ArgNo; in convertCallSiteObjects()
527 printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI); in convertCallSiteObjects()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp1128 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) in spillCalleeSavedRegisters()
1129 if (!MF.getRegInfo().isLiveIn(ArgReg)) in spillCalleeSavedRegisters()
1130 CopyRegs.insert(ArgReg); in spillCalleeSavedRegisters()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1472 unsigned ArgReg; in processCallArgs() local
1474 ArgReg = NextFPR++; in processCallArgs()
1478 ArgReg = NextGPR++; in processCallArgs()
1481 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg); in processCallArgs()
1482 RegArgs.push_back(ArgReg); in processCallArgs()
H A DPPCISelLowering.cpp7079 const MCPhysReg ArgReg = VA.getLocReg(); in LowerFormalArguments_AIX() local
7087 StackSize, mapArgRegToOffsetAIX(ArgReg, FL), /* IsImmutable */ false, in LowerFormalArguments_AIX()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp3012 Register ArgReg = getRegForValue(ArgVal); in processCallArgs() local
3013 if (!ArgReg) in processCallArgs()
3023 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
3024 if (!ArgReg) in processCallArgs()
3033 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3034 if (!ArgReg) in processCallArgs()
3045 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
3074 if (!emitStore(ArgVT, ArgReg, Addr, MMO)) in processCallArgs()
H A DAArch64ISelLowering.cpp6749 llvm::erase_if(CSInfo, [&VA](MachineFunction::ArgRegPair ArgReg) { in LowerCall() argument
6750 return ArgReg.Reg == VA.getLocReg(); in LowerCall()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp898 for (unsigned ArgReg : Args) in selectCall() local
899 MIB.addReg(ArgReg); in selectCall()
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DBugReporterVisitors.cpp3210 const MemRegion *ArgReg = Call->getArgSVal(Idx).getAsRegion(); in VisitNode() local
3214 if ( !ArgReg || !R->isSubRegionOf(ArgReg->StripCasts())) in VisitNode()
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.cpp813 for (const auto &ArgReg : CallFwdRegsInfo->second) { in collectCallSiteParameters() local
815 ForwardedRegWorklist.insert({ArgReg.Reg, {{ArgReg.Reg, EmptyExpr}}}) in collectCallSiteParameters()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp100 Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg(); in parametersInCSRMatch() local
101 if (MRI.getLiveInPhysReg(ArgReg) != Reg) in parametersInCSRMatch()