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Searched refs:ADDCARRY (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Daddcarry.ll4 ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
5 ; Signed fixed point multiplication eventually expands down to an ADDCARRY.
47 ; negative test for combineCarryDiamond(): ADDCARRY not legal
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h303 ADDCARRY, enumerator
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp73 case ISD::ADDCARRY: in Select()
H A DCSKYISelLowering.cpp54 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal); in CSKYTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h100 SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY, enumerator
H A DSystemZISelLowering.cpp188 setOperationAction(ISD::ADDCARRY, VT, Custom); in SystemZTargetLowering()
3994 while (Carry.getOpcode() == ISD::ADDCARRY) in isAddCarryChain()
4026 case ISD::ADDCARRY: in lowerADDSUBCARRY()
4030 BaseOp = SystemZISD::ADDCARRY; in lowerADDSUBCARRY()
5742 case ISD::ADDCARRY: in LowerOperation()
5936 OPCODE(ADDCARRY); in getTargetNodeName()
H A DSystemZOperators.td279 def z_addcarry_1 : SDNode<"SystemZISD::ADDCARRY", SDT_ZBinaryWithCarry>;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp543 case ISD::ADDCARRY: in Select()
905 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64 in SelectAddcSubb()
912 unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::S_ADD_CO_PSEUDO in SelectAddcSubb()
928 if ((IsAdd && (UI->getOpcode() != ISD::ADDCARRY)) || in SelectUADDO_USUBO()
H A DSIISelLowering.cpp229 setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i32, Legal); in SITargetLowering()
235 setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY}, MVT::i64, Legal); in SITargetLowering()
721 ISD::ADDCARRY, in SITargetLowering()
11004 Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY) in performAddCombine()
11020 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY; in performAddCombine()
11023 case ISD::ADDCARRY: { in performAddCombine()
11028 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args); in performAddCombine()
11061 Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::ADDCARRY : ISD::SUBCARRY; in performSubCombine()
11094 if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) || in performAddCarrySubCarryCombine()
11447 case ISD::ADDCARRY: in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp1765 SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo, in LowerUDIVREM64()
1767 SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi, in LowerUDIVREM64()
1779 SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo, in LowerUDIVREM64()
1781 SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Hi, in LowerUDIVREM64()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp305 case ISD::ADDCARRY: return "addcarry"; in getOperationName()
H A DLegalizeIntegerTypes.cpp187 case ISD::ADDCARRY: in PromoteIntegerResult()
1685 case ISD::ADDCARRY: in PromoteIntegerOperand()
2503 case ISD::ADDCARRY: in ExpandIntegerResult()
2908 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY, in ExpandIntRes_ADDSUB()
2917 : DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps); in ExpandIntRes_ADDSUB()
3084 CarryOp = ISD::ADDCARRY; in ExpandIntRes_UADDSUBO()
3160 unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY in ExpandIntRes_SADDSUBO_CARRY()
H A DDAGCombiner.cpp1688 case ISD::ADDCARRY: return visitADDCARRY(N); in visit()
2871 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(), in visitADDLikeCommutative()
2875 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitADDLikeCommutative()
2877 return DAG.getNode(ISD::ADDCARRY, DL, in visitADDLikeCommutative()
3019 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) in visitUADDOLike()
3143 if (Carry0.getOpcode() == ISD::ADDCARRY && in combineADDCARRYDiamond()
3160 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X, in combineADDCARRYDiamond()
3308 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), in visitADDCARRYLike()
3752 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) { in visitSUB()
3758 return DAG.getNode(ISD::ADDCARRY, DL, in visitSUB()
[all …]
H A DLegalizeDAG.cpp3451 case ISD::ADDCARRY: in ExpandNode()
3457 bool IsAdd = Node->getOpcode() == ISD::ADDCARRY; in ExpandNode()
H A DTargetLowering.cpp7074 Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next, in expandMUL_LOHI()
7088 Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi, in expandMUL_LOHI()
9219 unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY; in expandUADDSUBO()
H A DSelectionDAG.cpp3559 case ISD::ADDCARRY: in computeKnownBits()
3580 else if (Opcode == ISD::ADDCARRY || Opcode == ISD::SADDO_CARRY) in computeKnownBits()
4155 case ISD::ADDCARRY: in ComputeNumSignBits()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1553 setOperationAction(ISD::ADDCARRY, VT, Expand); in HexagonTargetLowering()
1556 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in HexagonTargetLowering()
3138 if (Opc == ISD::ADDCARRY) in LowerAddSubCarry()
3211 case ISD::ADDCARRY: in LowerOperation()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dsubcarry.ll343 ; Here %carryin is considered as valid carry flag for combining into ADDCARRY
H A Daddcarry.ll634 ; Here %carryin is considered as valid carry flag for combining into ADDCARRY
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp819 setOperationAction({ISD::ADDCARRY, ISD::SUBCARRY, ISD::SETCCCARRY, in initActions()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1126 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom); in ARMTargetLowering()
9735 if (Op.getOpcode() == ISD::ADDCARRY) { in LowerADDSUBCARRY()
10406 case ISD::ADDCARRY: in LowerOperation()
18191 Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry); in PerformCMOVCombine()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp645 case ISD::ADDCARRY: in IsProfitableToFold()
H A DX86ISelLowering.cpp2264 setOperationAction(ISD::ADDCARRY, VT, Custom); in X86TargetLowering()
31815 bool IsAdd = Opc == ISD::ADDCARRY || Opc == ISD::SADDO_CARRY; in LowerADDSUBCARRY()
32334 case ISD::ADDCARRY: in LowerOperation()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp568 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom); in AArch64TargetLowering()
569 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in AArch64TargetLowering()
5394 case ISD::ADDCARRY: in LowerOperation()