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Searched refs:hwip (Results 1 – 25 of 28) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.h38 u32 hwip; member
47 u32 hwip; member
54 uint32_t hwip; member
61 uint32_t hwip; member
71 uint32_t hwip; member
80 uint32_t hwip; member
94 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
98 (adev->reg_offset[entry.hwip][inst][entry.seg] + entry.reg_offset)
H A Dsoc15_common.h40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \
45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument
47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ argument
146 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
148 #define RREG32_RLC_NO_KIQ(reg, hwip) \ argument
149 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip, 0)
H A Damdgpu_aca.c176 struct aca_hwip *hwip; in aca_bank_hwip_is_matched() local
183 hwip = &aca_hwid_mcatypes[type]; in aca_bank_hwip_is_matched()
184 if (!hwip->hwid) in aca_bank_hwip_is_matched()
191 return hwip->hwid == hwid && hwip->mcatype == mcatype; in aca_bank_hwip_is_matched()
200 return handle->hwip == ACA_HWIP_TYPE_UMC; in aca_bank_is_valid()
202 if (!aca_bank_hwip_is_matched(bank, handle->hwip)) in aca_bank_is_valid()
645 handle->hwip = ras_info->hwip; in add_aca_handle()
H A Damdgpu_virt.h407 u32 acc_flags, u32 hwip, u32 xcc_id);
409 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
416 u32 acc_flags, u32 hwip,
H A Damdgpu_imu.h42 u32 hwip; member
H A Damdgpu_aca.h173 enum aca_hwip_type hwip; member
208 enum aca_hwip_type hwip; member
H A Damdgpu_ras.h386 #define AMDGPU_RAS_REG_ENTRY_OFFSET(hwip, ip_inst, segment, reg) \ argument
387 (adev->reg_offset[hwip][ip_inst][segment] + (reg))
397 uint32_t hwip; member
H A Damdgpu_virt.c1016 u32 acc_flags, u32 hwip, in amdgpu_virt_get_rlcg_reg_access_flag() argument
1021 switch (hwip) { in amdgpu_virt_get_rlcg_reg_access_flag()
1147 u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_wreg() argument
1155 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { in amdgpu_sriov_wreg()
1167 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id) in amdgpu_sriov_rreg() argument
1175 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) in amdgpu_sriov_rreg()
H A Dsoc15.c445 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
447 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
481 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
486 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
499 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
H A Dimu_v11_0_3.c117 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_rlc_ram_register_setting()
H A Dsoc24.c177 if (!adev->reg_offset[en->hwip][en->inst]) in soc24_read_register()
179 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc24_read_register()
H A Dsoc21.c311 if (!adev->reg_offset[en->hwip][en->inst]) in soc21_read_register()
313 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc21_read_register()
H A Dnv.c396 if (!adev->reg_offset[en->hwip][en->inst]) in nv_read_register()
398 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in nv_read_register()
H A Dimu_v12_0.c262 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_imu_rlc_ram_old()
H A Dimu_v11_0.c329 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in program_imu_rlc_ram()
H A Dumc_v12_0.c442 .hwip = ACA_HWIP_TYPE_UMC,
H A Dmmhub_v1_8.c800 .hwip = ACA_HWIP_TYPE_SMU,
H A Damdgpu_ras.c4824 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
4848 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
4925 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
4928 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, in amdgpu_ras_inst_reset_ras_error_count()
H A Djpeg_v4_0_3.c1373 .hwip = ACA_HWIP_TYPE_SMU,
H A Damdgpu_xgmi.c1190 .hwip = ACA_HWIP_TYPE_PCS_XGMI,
H A Damdgpu.h145 u32 hwip; member
H A Dgfx_v9_4_3.c910 .hwip = ACA_HWIP_TYPE_SMU,
1664 adev, entry->hwip, entry->instance) : in gfx_v9_4_3_check_rlcg_range()
1666 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + in gfx_v9_4_3_check_rlcg_range()
H A Dvcn_v4_0_3.c2010 .hwip = ACA_HWIP_TYPE_SMU,
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dcommon_baco.h47 uint32_t hwip; member
H A Dcommon_baco.c112 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] in soc15_baco_program_registers()

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