drm/amdgpu: add macro to calculate offset with instance

Add macro definition which calculate offset of the
register with index override.

This is useful in case when there is an array of
registers w

drm/amdgpu: add macro to calculate offset with instance

Add macro definition which calculate offset of the
register with index override.

This is useful in case when there is an array of
registers which is common for all instances.
To read registers in that case it is easy to define
registers once and the index value is manually passed
to calculate proper offset of register for each instance.

Signed-off-by: Sunil Khatri <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add support of gfx10 register dump

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri <[email protected]>
Reviewed

drm/amdgpu: add support of gfx10 register dump

Adding gfx10 gc registers to be used for register
dump via devcoredump during a gpu reset.

Signed-off-by: Sunil Khatri <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Read aquavanjaram PCIE register state

Add support to read aqua vanjaram PCIE register state

Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.

drm/amdgpu: Read aquavanjaram PCIE register state

Add support to read aqua vanjaram PCIE register state

Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Add soc config init for GC9.4.3 ASICs

Add function to initialize soc configuration information for GC 9.4.3
ASICs. Use it to map IPs and other SOC related information once IP
configurati

drm/amdgpu: Add soc config init for GC9.4.3 ASICs

Add function to initialize soc configuration information for GC 9.4.3
ASICs. Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.

For GC9.4.3 compute partition related callbacks are initialized as part
of configuration init.

Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add helpers to access registers on different AIDs

SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.

v2: put smn addressing of differ

drm/amdgpu: add helpers to access registers on different AIDs

SMN address which is larger than 32bit has different indications
through bit[34:32] on different AIDs.

v2: put smn addressing of different AIDs into asic specific place
v3: change to ext_id/ext_offset naming

Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init

New doorbell index assignment is used by aqua_vanjaram.

Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Sig

drm/amdgpu: switch to aqua_vanjaram_doorbell_index_init

New doorbell index assignment is used by aqua_vanjaram.

Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Add IP instance map for aqua vanjaram

Add XCC logical to physical instance map for aqua vanjaram

v2:
Keep look up table only for required IPs, for others return
default mapping (Felix)

drm/amdgpu: Add IP instance map for aqua vanjaram

Add XCC logical to physical instance map for aqua vanjaram

v2:
Keep look up table only for required IPs, for others return
default mapping (Felix).

Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add xcc index argument to soc15_grbm_select

To support grbm select for multiple XCD case.

v2: unify naming style

Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Hawking Zhang <Hawkin

drm/amdgpu: add xcc index argument to soc15_grbm_select

To support grbm select for multiple XCD case.

v2: unify naming style

Signed-off-by: Le Ma <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: drop soc15_set_ip_blocks()

No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <alexander.

drm/amdgpu: drop soc15_set_ip_blocks()

No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu/soc15: export common IP functions

So they can be driven by IP discovery table.

Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: make soc15_common_ip_funcs static

It's not used outside of soc15.c

Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

drm/amdgpu: refine ras codes for GC utc of aldebaran

The bank number of both VML2 and ATCL2 are changed to 8, so refine
related codes to avoid defining long name arrays.

Signed-off-by: Dennis Li <D

drm/amdgpu: refine ras codes for GC utc of aldebaran

The bank number of both VML2 and ATCL2 are changed to 8, so refine
related codes to avoid defining long name arrays.

Signed-off-by: Dennis Li <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add ras support for gfx of aldebaran

add edc counter/status reset and query functions for gfx block of
aldebaran.

v2: change to clear edc counter explicitly
aldebaran hardware will not

drm/amdgpu: add ras support for gfx of aldebaran

add edc counter/status reset and query functions for gfx block of
aldebaran.

v2: change to clear edc counter explicitly
aldebaran hardware will not clear edc counter after driver reading them,
so driver should clear them explicitly.

Signed-off-by: Dennis Li <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add register base init for aldebaran (v2)

v1: add aldebaran_reg_base_init function to initialize
register base for aldebaran (Le)
v2: update VCN HWIP and initialize base offset (James)

drm/amdgpu: add register base init for aldebaran (v2)

v1: add aldebaran_reg_base_init function to initialize
register base for aldebaran (Le)
v2: update VCN HWIP and initialize base offset (James)

Signed-off-by: Le Ma <[email protected]>
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Acked-by: Evan Quan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: request init data in virt detection

Move request init data to virt detection func, so we
can insert request full access between request init data
and set ip blocks.

Signed-off-by: Wenhu

drm/amdgpu: request init data in virt detection

Move request init data to virt detection func, so we
can insert request full access between request init data
and set ip blocks.

Signed-off-by: Wenhui Sheng <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: revise RLCG access path

what changed:
1)provide new implementation interface for the rlcg access path
2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op
function can acc

drm/amdgpu: revise RLCG access path

what changed:
1)provide new implementation interface for the rlcg access path
2)put SQ_CMD/SQ_IND_INDEX to GFX9 RLCG path to let debugfs's reg_op
function can access reg that need RLCG path help

now even debugfs's reg_op can used to dump wave.

tested-by: Monk Liu <[email protected]>
tested-by: Zhou pengju <[email protected]>
Signed-off-by: Zhou pengju <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Emily Deng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10

It may lose gpuvm invalidate acknowldege state across power-gating off
cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema

drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10

It may lose gpuvm invalidate acknowldege state across power-gating off
cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
before invalidation and semaphore release after invalidation.

After adding semaphore acquire before invalidation, the semaphore
register become read-only if another process try to acquire semaphore.
Then it will not be able to release this semaphore. Then it may cause
deadlock problem. If this deadlock problem happens, it needs a semaphore
firmware fix.

Signed-off-by: changzhu <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: define soc15_ras_field_entry for reuse

The struct soc15_ras_field_entry will be reused by
other IPs, such as mmhub and gc

v2: rename ras_subblock_regs to gc_ras_fields_vg20,
because the

drm/amdgpu: define soc15_ras_field_entry for reuse

The struct soc15_ras_field_entry will be reused by
other IPs, such as mmhub and gc

v2: rename ras_subblock_regs to gc_ras_fields_vg20,
because the future asic maybe have a different table.

Signed-off-by: Dennis Li <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10

It may lose gpuvm invalidate acknowldege state across power-gating off
cycle. To avoid this issue in gmc9/gmc10 invalidation, add sema

drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10

It may lose gpuvm invalidate acknowldege state across power-gating off
cycle. To avoid this issue in gmc9/gmc10 invalidation, add semaphore acquire
before invalidation and semaphore release after invalidation.

After adding semaphore acquire before invalidation, the semaphore
register become read-only if another process try to acquire semaphore.
Then it will not be able to release this semaphore. Then it may cause
deadlock problem. If this deadlock problem happens, it needs a semaphore
firmware fix.

Signed-off-by: changzhu <[email protected]>
Acked-by: Huang Rui <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]

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drm/amdgpu: change to query the actual EDC counter

For the potential request in the future, change to
query the actual EDC counter.

Signed-off-by: Dennis Li <[email protected]>
Reviewed-by: Hawking

drm/amdgpu: change to query the actual EDC counter

For the potential request in the future, change to
query the actual EDC counter.

Signed-off-by: Dennis Li <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Tao Zhou <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: dynamically initialize IP offset for Arcturus

Add support for the IP offsets on Arcturus.

Signed-off-by: Le Ma <[email protected]>
Acked-by: Snow Zhang < [email protected]>
Signed-off-by:

drm/amdgpu: dynamically initialize IP offset for Arcturus

Add support for the IP offsets on Arcturus.

Signed-off-by: Le Ma <[email protected]>
Acked-by: Snow Zhang < [email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10

Move to the header file.

Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Alex Deucher <[email protected]>

drm/amdgpu: avoid to use SOC15_REG_OFFSET in static array for navi10

Move to the header file.

Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Fixed missing to clear some EDC count

EDC counts are related to instance and se. They are not the same
for different type of EDC. EDC clearing are changed to base on
individual EDC's ins

drm/amdgpu: Fixed missing to clear some EDC count

EDC counts are related to instance and se. They are not the same
for different type of EDC. EDC clearing are changed to base on
individual EDC's instance and SE number.

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled

When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.

Si

drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled

When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.

Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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drm/amdgpu: Doorbell layout for vega20 and future asic

This introduces new doorbell layout for vega20 and future asics

v2: Use enum definition instead of hardcoded value

Signed-off-by: Oak Zeng <o

drm/amdgpu: Doorbell layout for vega20 and future asic

This introduces new doorbell layout for vega20 and future asics

v2: Use enum definition instead of hardcoded value

Signed-off-by: Oak Zeng <[email protected]>
Suggested-by: Felix Kuehling <[email protected]>
Suggested-by: Alex Deucher <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

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