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Searched refs:getReg (Results 1 – 25 of 664) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
436 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
471 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
507 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
545 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
576 AccName = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp868 Builder.buildCopy(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); in applySextTruncSextLoad()
2584 .getReg(0); in applyCombineTruncOfShift()
2671 return MOP1.getReg() == MOP2.getReg(); in matchEqualDefs()
5525 {FpExtX.getReg(0), FpExtY.getReg(0), RHS.Reg}); in matchCombineFAddFpExtFMulToFMadOrFMA()
5540 {FpExtX.getReg(0), FpExtY.getReg(0), LHS.Reg}); in matchCombineFAddFpExtFMulToFMadOrFMA()
5781 B.buildFNeg(DstTy, RHS.MI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFMulToFMadOrFMA()
5814 B.buildFNeg(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFNegFMulToFMadOrFMA()
5860 B.buildFPExt(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5862 B.buildFPExt(DstTy, FMulMI->getOperand(2).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
5876 B.buildFPExt(DstTy, FMulMI->getOperand(1).getReg()).getReg(0); in matchCombineFSubFpExtFMulToFMadOrFMA()
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H A DGISelKnownBits.cpp62 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
229 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
332 computeKnownBitsMin(MI.getOperand(2).getReg(), MI.getOperand(3).getReg(), in computeKnownBitsImpl()
457 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
520 Register SrcReg = MI.getOperand(1).getReg(); in computeKnownBitsImpl()
581 if (MI.getOperand(1).getReg() == R) { in computeKnownBitsImpl()
641 MRI.getType(Src.getReg()).isValid()) { in computeNumSignBits()
649 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
657 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
681 Register Src = MI.getOperand(1).getReg(); in computeNumSignBits()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp168 Register Reg = Op.getReg(); in applyBank()
940 .getReg(0); in executeInWaterfallLoop()
1633 .getReg(0); in applyMappingMAD_64_32()
1666 DstLo = AddLo.getReg(0); in applyMappingMAD_64_32()
1672 DstHi = AddHi.getReg(0); in applyMappingMAD_64_32()
1729 return std::pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1735 return std::pair(ExtLo.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1739 return std::pair(Bitcast.getReg(0), ShiftHi.getReg(0)); in unpackV2S16ToS32()
1779 .getReg(0); in handleD16VData()
2507 B.buildBuildVectorTrunc(DstReg, {Lo.getReg(0), Hi.getReg(0)}); in applyMappingImpl()
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H A DSIOptimizeExecMasking.cpp105 return MI.getOperand(0).getReg(); in isCopyFromExec()
120 return MI.getOperand(1).getReg(); in isCopyToExec()
145 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
148 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
161 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
164 return MI.getOperand(0).getReg(); in isLogicalOpOnExec()
558 .addReg(OtherOp->getReg()); in optimizeExecSequence()
672 {Exec, SaveExecSrc0->getReg()}); in tryRecordVCmpxAndSaveexecSequence()
740 (XorSrc0.getReg() == Exec || XorSrc1.getReg() == Exec)) { in tryRecordOrSaveexecXorSequence()
754 if ((XorSrc0.getReg() == Exec && XorSrc1.getReg() == OrDst.getReg()) || in tryRecordOrSaveexecXorSequence()
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H A DAMDGPULegalizerInfo.cpp2494 auto X = B.buildXor(S32, Unmerge.getReg(0), Unmerge.getReg(1)); in legalizeITOFP()
3186 return {ScaledInput.getReg(0), IsLtSmallestNormal.getReg(0)}; in getScaledLogInput()
3321 getMad(B, Ty, YH.getReg(0), CT.getReg(0), YTCT.getReg(0), Flags); in legalizeFlogCommon()
3323 R = getMad(B, Ty, YH.getReg(0), CH.getReg(0), Mad1, Flags); in legalizeFlogCommon()
3593 getMad(B, Ty, XL.getReg(0), CH.getReg(0), XLCL.getReg(0), Flags); in legalizeFExp()
3594 PL = getMad(B, Ty, XH.getReg(0), CL.getReg(0), Mad0, Flags); in legalizeFExp()
3751 Src0 = B.buildTrunc(S16, MI.getOperand(1).getReg()).getReg(0); in legalizeBuildVector()
3752 Src1 = B.buildTrunc(S16, MI.getOperand(2).getReg()).getReg(0); in legalizeBuildVector()
4437 return {ResultLo.getReg(0), ResultHi.getReg(0)}; in emitReciprocalU64()
5529 .getReg(0); in handleD16VData()
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H A DSIShrinkInstructions.cpp99 Register Reg = Src0.getReg(); in foldImmediates()
150 Register Reg = MO.getReg(); in shouldShrinkTrue16()
472 MI.getOperand(0).getReg()) in shrinkMadFma()
531 MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
532 MRI->setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
536 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
648 Register X = Xop.getReg(); in matchSwap()
762 Register SDstReg = Op->getReg(); in tryReplaceDeadSDST()
837 MRI->setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
838 MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp269 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
270 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
290 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
766 .getReg(0); in applyDupLane()
943 .getReg(0); in getVectorFCMP()
950 .getReg(0); in getVectorFCMP()
957 .getReg(0); in getVectorFCMP()
964 .getReg(0); in getVectorFCMP()
971 .getReg(0); in getVectorFCMP()
1004 Register Dst = CmpMI.getReg(0); in applyLowerVectorFCMP()
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H A DAArch64PreLegalizerCombiner.cpp52 Register DstReg = MI.getOperand(0).getReg(); in matchFConstantToConstant()
84 Register LHS = MI.getOperand(2).getReg(); in matchICmpRedundantTrunc()
89 Register RHS = MI.getOperand(3).getReg(); in matchICmpRedundantTrunc()
154 Register Dst = MI.getOperand(0).getReg(); in matchFoldGlobalOffset()
310 .getReg(); in applyExtAddvToUdotAddv()
357 .getReg(); in applyExtAddvToUdotAddv()
363 .getReg(0)); in applyExtAddvToUdotAddv()
368 .getReg(0)); in applyExtAddvToUdotAddv()
397 .getReg(0)); in applyExtAddvToUdotAddv()
505 .getReg(0); in applyExtUaddvToUaddlv()
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H A DAArch64InstructionSelector.cpp704 return RegSequence.getReg(0); in createTuple()
966 Register Reg = MO.getReg(); in selectDebugInstr()
1673 emitFPCompare(FCmp.getOperand(2).getReg(), FCmp.getOperand(3).getReg(), MIB, in selectCompareBranchFedByFCmp()
2198 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()}); in earlySelectSHL()
3482 if (!emitFPCompare(I.getOperand(2).getReg(), I.getOperand(3).getReg(), MIB, in select()
5136 emitSelect(I.getOperand(0).getReg(), I.getOperand(2).getReg(), in tryOptSelect()
5265 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()}); in selectShuffleVector()
6050 .getReg(); in selectVectorLoadLaneIntrinsic()
6117 .getReg(); in selectVectorStoreLaneIntrinsic()
6153 {I.getOperand(0).getReg(), I.getOperand(1).getReg()}, in selectIntrinsicWithSideEffects()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp212 Register Reg = Op->getReg(); in getVRegDefOrNull()
481 addRegToUpdate(MO.getReg()); in simplifyCode()
506 Register RegToUpdate = MO.getReg(); in simplifyCode()
663 MI.getOperand(0).getReg()) in simplifyCode()
1187 MI.getOperand(0).getReg()) in simplifyCode()
1189 addRegToUpdate(Op1.getReg()); in simplifyCode()
1190 addRegToUpdate(Op2.getReg()); in simplifyCode()
1220 DstReg = MI.getOperand(1).getReg(); in simplifyCode()
1787 addRegToUpdate(MO.getReg()); in eliminateRedundantCompare()
1790 addRegToUpdate(MO.getReg()); in eliminateRedundantCompare()
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H A DPPCMacroFusion.cpp77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
109 return RA.getReg().isVirtual() || in checkOpConstraints()
110 (RA.getReg() != PPC::ZERO && RA.getReg() != PPC::ZERO8); in checkOpConstraints()
119 if (!RT.getReg().isVirtual()) in checkOpConstraints()
123 (RT.getReg() == PPC::ZERO || RT.getReg() == PPC::ZERO8)) in checkOpConstraints()
172 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
183 if (!BT.isReg() || (!BT.getReg().isVirtual() && BT.getReg() != PPC::CR0)) in checkOpConstraints()
209 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
220 if (RA.getReg() == PPC::ZERO || RA.getReg() == PPC::ZERO8) in checkOpConstraints()
H A DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp631 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
673 if (!MOUse.getReg()) in forwardUses()
696 if (MOUse.getReg() != CopyDstReg) { in forwardUses()
863 Register Reg = MO.getReg(); in ForwardCopyPropagateBlock()
980 if (!MODef.getReg()) in propagateDefs()
997 if (MODef.getReg() != Src) in propagateDefs()
1064 if (!MO.getReg()) in BackwardCopyPropagateBlock()
1264 return SpillCopy->Source->getReg() == ReloadCopy->Destination->getReg() && in EliminateSpillageCopies()
1265 SpillCopy->Destination->getReg() == ReloadCopy->Source->getReg(); in EliminateSpillageCopies()
1278 return PrevCopy->Source->getReg() == CurrentCopy->Destination->getReg(); in EliminateSpillageCopies()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGenericMachineInstrs.h32 Register getReg(unsigned Idx) const { return getOperand(Idx).getReg(); } in getReg() function
292 Register getBaseReg() const { return getReg(1); } in getBaseReg()
293 Register getOffsetReg() const { return getReg(2); } in getOffsetReg()
311 Register getCondReg() const { return getReg(1); } in getCondReg()
312 Register getTrueReg() const { return getReg(2); } in getTrueReg()
313 Register getFalseReg() const { return getReg(3); } in getFalseReg()
326 Register getLHSReg() const { return getReg(2); } in getLHSReg()
327 Register getRHSReg() const { return getReg(3); } in getRHSReg()
358 Register getDstReg() const { return getReg(0); } in getDstReg()
436 Register getCarryInReg() const { return getReg(4); } in getCarryInReg()
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H A DLegalizationArtifactCombiner.h66 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
575 if (Def.getReg() == SearchDef) in getDefIndex()
659 return BV.getReg(0); in findValueFromBuildVector()
678 return BV.getReg(StartSrcIdx); in findValueFromBuildVector()
821 if (MO.getReg() == DefReg) in findValueFromDefImpl()
879 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeDefs()
952 Register Dst = MI.getReg(0); in tryCombineMergeLike()
1048 LLT DestTy = MRI.getType(MI.getReg(0)); in tryCombineUnmergeValues()
1092 Register Def = MI.getReg(I); in tryCombineUnmergeValues()
1189 Register DefReg = MI.getReg(DefIdx); in tryCombineUnmergeValues()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp107 printRegName(O, Dst.getReg()); in printInst()
109 printRegName(O, MO1.getReg()); in printInst()
112 printRegName(O, MO2.getReg()); in printInst()
129 printRegName(O, Dst.getReg()); in printInst()
313 unsigned Reg = Op.getReg(); in printOperand()
442 if (!MO2.getReg()) { in printAM2PreOrOffsetIndexOp()
517 if (!MO1.getReg()) { in printAddrMode2OffsetOperand()
547 if (MO2.getReg()) { in printAM3PreOrOffsetIndexOp()
588 if (MO1.getReg()) { in printAddrMode3OffsetOperand()
738 if (MO.getReg() == 0) in printAddrMode6OffsetOperand()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp231 if (MI.getOperand(1).getReg() != AArch64::WZR) in visitORR()
274 Register DefReg = MI.getOperand(0).getReg(); in visitORR()
275 Register SrcReg = MI.getOperand(2).getReg(); in visitORR()
295 Register DstReg = MI.getOperand(0).getReg(); in visitINSERT()
369 MI.getOperand(1).getReg() == AArch64::WZR) in visitADDSUB()
405 MI.getOperand(1).getReg() == AArch64::WZR) in visitADDSSUBS()
532 Register DstReg = MI.getOperand(0).getReg(); in splitTwoPartImm()
533 Register SrcReg = MI.getOperand(1).getReg(); in splitTwoPartImm()
596 Register DstReg = MI.getOperand(0).getReg(); in visitINSviGPR()
664 Register OldDef = MI.getOperand(0).getReg(); in visitINSvi64lane()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp240 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
285 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
298 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
305 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
365 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
379 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
381 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
403 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
425 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
440 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp69 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
70 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
123 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
125 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
133 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
135 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
232 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
233 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
241 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
895 if (!MCOp.getReg()) in printOperand()
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H A DSystemZTargetStreamer.h37 if (A.getOperand(0).getReg() != B.getOperand(0).getReg()) in operator()
38 return A.getOperand(0).getReg() < B.getOperand(0).getReg(); in operator()
41 if (A.getOperand(3).getReg() != B.getOperand(3).getReg()) in operator()
42 return A.getOperand(3).getReg() < B.getOperand(3).getReg(); in operator()
H A DSystemZShortenInst.cpp79 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
111 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
121 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
185 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
186 SystemZMC::getFirstReg(LHSMO.getReg()) < 16 && in shortenFusedFPOp()
187 SystemZMC::getFirstReg(RHSMO.getReg()) < 16 && in shortenFusedFPOp()
188 SystemZMC::getFirstReg(AccMO.getReg()) < 16 && in shortenFusedFPOp()
189 DstMO.getReg() == AccMO.getReg()) { in shortenFusedFPOp()
359 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) && in processBlock()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp57 GR->add(GV, &MF, MI.getOperand(2).getReg()); in addConstantsToTrack()
85 Register Reg = MI->getOperand(2).getReg(); in addConstantsToTrack()
135 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
138 Register Def = MI.getOperand(0).getReg(); in insertBitcasts()
139 Register Source = MI.getOperand(2).getReg(); in insertBitcasts()
174 Register Reg = MI->getOperand(0).getReg(); in propagateSPIRVType()
266 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
279 Register Reg = MI.getOperand(1).getReg(); in generateAssignInstrs()
295 Register Reg = MI.getOperand(0).getReg(); in generateAssignInstrs()
487 Register Dst = MI.getOperand(0).getReg(); in processSwitches()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
260 Register T = MO.getReg(); in partitionRegisters()
500 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
536 Register R = MD.getReg(); in collectIndRegsForLoop()
600 Register R = Op.getReg(); in createHalfInstr()
674 .addReg(AdrOp.getReg(), RSA) in splitMemRef()
808 .addReg(Op1.getReg(), RS, HiSR); in splitShift()
944 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
958 .addReg(Op1.getReg(), RS1, HiSR) in splitAslOr()
1077 Register R = Op.getReg(); in replaceSubregUses()
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12345678910>>...27