99     Register Reg = Src0.getReg();  in foldImmediates()
150       Register Reg = MO.getReg();  in shouldShrinkTrue16()
321     unsigned Vgpr = TRI->getHWRegIndex(Op.getReg());  in shrinkMIMG()
322     unsigned Dwords = TRI->getRegSizeInBits(Op.getReg(), *MRI) / 32;  in shrinkMIMG()
407     if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg()))  in shrinkMadFma()
409     else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg()))  in shrinkMadFma()
435   if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) {  in shrinkMadFma()
472             MI.getOperand(0).getReg())  in shrinkMadFma()
530     if (Dest->getReg().isVirtual() && SrcReg->isReg()) {  in shrinkScalarLogicOp()
531       MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg());  in shrinkScalarLogicOp()
532       MRI->setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg());  in shrinkScalarLogicOp()
536     if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {  in shrinkScalarLogicOp()
544         MI.getOperand(2).ChangeToRegister(Dest->getReg(), /*IsDef*/ false,  in shrinkScalarLogicOp()
566     if (Reg.isPhysical() && MO.getReg().isPhysical()) {  in instAccessReg()
567       if (TRI->regsOverlap(Reg, MO.getReg()))  in instAccessReg()
569     } else if (MO.getReg() == Reg && Reg.isVirtual()) {  in instAccessReg()
613             TII->get(AMDGPU::IMPLICIT_DEF), Op.getReg());  in dropInstructionKeepingImpDefs()
642   Register T = MovT.getOperand(0).getReg();  in matchSwap()
648   Register X = Xop.getReg();  in matchSwap()
669         MovY->getOperand(1).getReg() != T   ||  in matchSwap()
673     Register Y = MovY->getOperand(0).getReg();  in matchSwap()
698           I->getOperand(0).getReg() != X ||  in matchSwap()
743         if (Op.isKill() && TRI->regsOverlap(X, Op.getReg()))  in matchSwap()
762   Register SDstReg = Op->getReg();  in tryReplaceDeadSDST()
803         if (Src.isImm() && MI.getOperand(0).getReg().isPhysical()) {  in runOnMachineFunction()
836         if (Dest->getReg().isVirtual() && Src0->isReg()) {  in runOnMachineFunction()
837           MRI->setRegAllocationHint(Dest->getReg(), 0, Src0->getReg());  in runOnMachineFunction()
838           MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());  in runOnMachineFunction()
842         if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {  in runOnMachineFunction()
865         if (Src.isImm() && Dst.getReg().isPhysical()) {  in runOnMachineFunction()
931           Register DstReg = Op0.getReg();  in runOnMachineFunction()
957         Register SReg = Src2->getReg();  in runOnMachineFunction()
973         if (SDst->getReg() != VCCReg) {  in runOnMachineFunction()
974           if (SDst->getReg().isVirtual())  in runOnMachineFunction()
975             MRI->setRegAllocationHint(SDst->getReg(), 0, VCCReg);  in runOnMachineFunction()
983         if (Src2 && Src2->getReg() != VCCReg) {  in runOnMachineFunction()
984           if (Src2->getReg().isVirtual())  in runOnMachineFunction()
985             MRI->setRegAllocationHint(Src2->getReg(), 0, VCCReg);  in runOnMachineFunction()