Lines Matching refs:getReg
42 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
46 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
47 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
56 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
60 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
61 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
69 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
70 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
71 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
122 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
123 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
125 .addReg(MI->getOperand(3).getReg()); in lowerSubvectorLoad()
132 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorStore()
133 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
135 .addReg(MI->getOperand(3).getReg()) in lowerSubvectorStore()
232 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
233 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
241 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
242 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
250 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
259 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
268 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
269 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
277 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
278 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
286 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
295 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
314 .addReg(MI->getOperand(0).getReg())); in emitInstruction()
321 .addReg(MI->getOperand(0).getReg())); in emitInstruction()
330 Register TargetReg = MI->getOperand(0).getReg(); in emitInstruction()
332 Register ADAReg = MI->getOperand(2).getReg(); in emitInstruction()
371 .addReg(MI->getOperand(0).getReg()); in emitInstruction()
388 .addReg(MI->getOperand(0).getReg()); in emitInstruction()
395 .addReg(MI->getOperand(2).getReg()); in emitInstruction()
400 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
401 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
403 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
409 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
410 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
412 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
418 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
421 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
427 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
430 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
436 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
437 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
439 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
445 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
446 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
448 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
454 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
457 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
463 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
466 .addReg(MI->getOperand(3).getReg()) in emitInstruction()
486 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
492 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in emitInstruction()
498 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in emitInstruction()
514 .addReg(MI->getOperand(0).getReg()) in emitInstruction()
515 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg())) in emitInstruction()
516 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); in emitInstruction()
522 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
523 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())); in emitInstruction()
564 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg())) in emitInstruction()
565 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())) in emitInstruction()
571 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
572 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in emitInstruction()
573 .addReg(MI->getOperand(1).getReg()) in emitInstruction()
664 Register LenMinus1Reg = MI->getOperand(1).getReg(); in emitInstruction()
665 Register DestReg = MI->getOperand(2).getReg(); in emitInstruction()
667 Register SrcReg = MI->getOperand(4).getReg(); in emitInstruction()
805 ScratchReg = MI.getOperand(ScratchIdx).getReg(); in LowerPATCHPOINT()
895 if (!MCOp.getReg()) in printOperand()
898 printFormattedRegName(MAI, MCOp.getReg(), OS); in printOperand()
932 SystemZ::GR128BitRegClass.contains(MO.getReg())) in PrintAsmOperand()
934 MCOperand::createReg(MRI.getSubReg(MO.getReg(), SystemZ::subreg_l64)); in PrintAsmOperand()
949 printAddress(MAI, MI->getOperand(OpNo).getReg(), in PrintAsmMemoryOperand()
951 MI->getOperand(OpNo + 2).getReg(), OS); in PrintAsmMemoryOperand()
1262 unsigned Reg = CS.getReg(); in emitPPA1()