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Searched refs:VT (Results 1 – 25 of 319) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp705 if (VT != MVT::i32 && VT != MVT::i64) in SelectShiftedRegisterFromAnd()
3090 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOrAndImm()
3354 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertOpFromOr()
3550 if (VT != MVT::i32 && VT != MVT::i64) in tryBitfieldInsertInZeroOp()
6425 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
6429 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
6433 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
6444 } else if (VT == MVT::v8i16 || VT == MVT::v4i16 || VT == MVT::v4f16 || in Select()
6448 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
6452 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
H A DAArch64ISelLowering.cpp1218 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32) { in AArch64TargetLowering()
1682 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) { in addTypeForNEON()
1695 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64 || in addTypeForNEON()
1737 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
10101 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) { in LowerVAARG()
10300 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 || in getEstimate()
13509 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 && in LowerEXTRACT_VECTOR_ELT()
16310 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
16753 if (VT != MVT::v8i16 && VT != MVT::v4i32 && VT != MVT::v2i64) in performUADDVZextCombine()
17015 if (VT != MVT::v8i16 && VT != MVT::v4i32 && VT != MVT::v2i64) in performMulVectorExtendCombine()
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H A DAArch64FastISel.cpp396 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
564 MVT VT; in fastMaterializeFloatZero() local
568 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
1018 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1889 MVT VT; in selectAddSub() local
2941 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2943 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2974 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
3194 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3321 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
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/freebsd-14.2/contrib/llvm-project/llvm/utils/TableGen/
H A DVTEmitter.cpp37 for (auto *VT : ValueTypes) { in run() local
38 auto Number = VT->getValueAsInt("Value"); in run()
42 VTsByNumber[Number] = VT; in run()
66 for (const auto *VT : VTsByNumber) { in run() local
67 if (!VT) in run()
70 auto Value = VT->getValueAsInt("Value"); in run()
72 bool IsFP = VT->getValueAsInt("isFP"); in run()
94 << VT->getValueAsInt("Size") << ", " in run()
113 for (const auto *VT : VTsByNumber) { in run() local
114 if (!VT || !VT->getValueAsInt("isVector")) in run()
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/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h44 bool operator==(EVT VT) const {
45 return !(*this != VT);
239 bool bitsEq(EVT VT) const { in bitsEq()
267 bool bitsGT(EVT VT) const { in bitsGT()
271 return knownBitsGT(VT); in bitsGT()
275 bool bitsGE(EVT VT) const { in bitsGE()
279 return knownBitsGE(VT); in bitsGE()
283 bool bitsLT(EVT VT) const { in bitsLT()
287 return knownBitsLT(VT); in bitsLT()
291 bool bitsLE(EVT VT) const { in bitsLE()
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H A DTargetLowering.h720 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE; in hasFastEqualityCompare()
1107 return VT; in getTypeToExpandTo()
1109 VT = getTypeToTransformTo(Context, VT); in getTypeToExpandTo()
1281 return (VT == MVT::Other || isTypeLegal(VT)) &&
1295 return (VT == MVT::Other || isTypeLegal(VT)) &&
1309 return (VT == MVT::Other || isTypeLegal(VT)) &&
1380 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand); in isOperationExpand()
1385 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegal()
1567 assert((VT.isInteger() || VT.isFloatingPoint()) && in getTypeToPromoteTo()
1570 MVT NVT = VT; in getTypeToPromoteTo()
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H A DMachineValueType.h378 bool knownBitsGT(MVT VT) const { in knownBitsGT() argument
384 bool knownBitsGE(MVT VT) const { in knownBitsGE() argument
400 bool bitsGT(MVT VT) const { in bitsGT() argument
403 return knownBitsGT(VT); in bitsGT()
407 bool bitsGE(MVT VT) const { in bitsGE() argument
410 return knownBitsGE(VT); in bitsGE()
414 bool bitsLT(MVT VT) const { in bitsLT() argument
417 return knownBitsLT(VT); in bitsLT()
421 bool bitsLE(MVT VT) const { in bitsLE() argument
424 return knownBitsLE(VT); in bitsLE()
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H A DSelectionDAG.h113 FastID(ID), VTs(VT), NumVTs(Num) {
639 SDVTList getVTList(EVT VT);
661 return getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT,
726 return getFrameIndex(FI, VT, true);
847 (VT.isInteger() &&
863 (VT.isInteger() &&
878 return VT.isScalableVector() ?
879 getSplatVector(VT, DL, Op) : getSplatBuildVector(VT, DL, Op);
969 return IsSigned ? getSExtOrTrunc(Op, DL, VT) : getZExtOrTrunc(Op, DL, VT);
1097 SDValue getUNDEF(EVT VT) {
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp22 LLVMContext &Context, CallingConv::ID CC, EVT VT) const { in getNumRegistersForCallingConv()
26 if (VT.isVector() && VT.getVectorNumElements() == 3 && in getNumRegistersForCallingConv()
27 (VT.getVectorElementType() == MVT::i1 || in getNumRegistersForCallingConv()
28 VT.getVectorElementType() == MVT::i8)) in getNumRegistersForCallingConv()
30 if (!VT.isVector() && VT.isInteger() && VT.getSizeInBits() <= 64) in getNumRegistersForCallingConv()
32 return getNumRegisters(Context, VT); in getNumRegistersForCallingConv()
37 EVT VT) const { in getRegisterTypeForCallingConv()
41 if (VT.isVector() && VT.getVectorNumElements() == 3) { in getRegisterTypeForCallingConv()
42 if (VT.getVectorElementType() == MVT::i1) in getRegisterTypeForCallingConv()
44 else if (VT.getVectorElementType() == MVT::i8) in getRegisterTypeForCallingConv()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp227 VT = LVT; in findOptimalMemOpLowering()
240 if (VT.isVector() || VT.isFloatingPoint()) { in findOptimalMemOpLowering()
311 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) in softenSetCCOperands()
1060 NVT = VT; in combineShiftToAVG()
5038 (VT == ShValTy || (isTypeLegal(VT) && VT.bitsLE(ShValTy))) && in SimplifySetCC()
6169 if (VT.isVector() || !VT.isSimple()) in BuildSDIV()
6331 if (VT.isVector() || !VT.isSimple()) in BuildUDIV()
8915 ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), in expandCTTZ()
9466 if (VT.isFloatingPoint() || VT.isVector()) { in expandUnalignedLoad()
10355 DAG.getVTList(VT, VT), in expandFixedPointDiv()
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H A DDAGCombiner.cpp1593 if (VT.isVector() || !VT.isInteger()) in PromoteIntBinOp()
1661 if (VT.isVector() || !VT.isInteger()) in PromoteIntShiftOp()
1710 if (VT.isVector() || !VT.isInteger()) in PromoteExtend()
1741 if (VT.isVector() || !VT.isInteger()) in PromoteLoad()
4632 if (VT.isVector() || !VT.isInteger()) in useDivRem()
5379 if (VT.isSimple() && !VT.isVector()) { in visitSMUL_LOHI()
5433 if (VT.isSimple() && !VT.isVector()) { in visitUMUL_LOHI()
7371 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) in MatchBSwapHWordLow()
9097 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64) in MatchLoadCombine()
22749 if (InVT1 != VT || InVT2 != VT) { in createBuildVecShuffle()
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H A DSelectionDAG.cpp1120 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
1562 SDValue TrueValue = getBoolConstant(true, DL, VT, VT); in getLogicalNOT()
1568 SDValue TrueValue = getBoolConstant(true, DL, VT, VT); in getVPLogicalNOT()
1941 if (VT.isSimple() && (unsigned)VT.getSimpleVT().SimpleTy >= in getValueType()
2426 if (TLI->isTypeLegal(VT) || !VT.isVector()) in getReducedAlign()
5657 assert((!VT.isVector() || VT.getVectorElementCount() == in getNode()
5682 assert((!VT.isVector() || VT.getVectorElementCount() == in getNode()
5699 assert((!VT.isVector() || VT.getVectorElementCount() == in getNode()
6720 assert((!VT.isVector() || VT == N2.getValueType()) && in getNode()
7307 if (VT != Value.getValueType() && !VT.isInteger()) in getMemsetValue()
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H A DLegalizeVectorOps.cpp770 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
1153 EVT VT = Node->getValueType(0); in ExpandSELECT() local
1206 EVT VT = Node->getValueType(0); in ExpandSEXTINREG() local
1236 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1257 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
1295 if (SrcVT.bitsLE(VT)) { in ExpandZERO_EXTEND_VECTOR_INREG()
1332 if (VT.isScalableVector()) in ExpandBSWAP()
1365 if (VT.isScalableVector()) { in ExpandBITREVERSE()
1427 EVT VT = Mask.getValueType(); in ExpandVSELECT() local
1478 EVT VT = Mask.getValueType(); in ExpandVP_SELECT() local
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8172 if (VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 || in LowerToHorizontalOp()
8305 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) in materializeVectorConstant()
27985 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) { in LowerABS()
29784 (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) && in LowerFunnelShift()
33813 VT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd()
39572 if (VT != MVT::v4f32 && VT != MVT::v8f32 && VT != MVT::v16f32) in combineCommutableSHUFP()
46775 (!VT.isVector() || !VT.isSimple() || !VT.isInteger())) in combineMul()
50416 if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT && in combineStore()
51738 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32 && in combineXorSubCTLZ()
57202 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f80) in getRegForInlineAsmConstraint()
[all …]
H A DX86InterleavedAccess.cpp229 static MVT scaleVectorType(MVT VT) { in scaleVectorType() argument
260 assert(VT.getSizeInBits() >= 256 && in genShuffleBland()
327 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
368 MVT HalfVT = scaleVectorType(VT); in interleave8bitStride4()
417 if (VT == MVT::v16i8) { in interleave8bitStride4()
438 int VectorSize = VT.getSizeInBits(); in createShuffleStride()
439 int VF = VT.getVectorNumElements(); in createShuffleStride()
560 createShuffleStride(VT, 3, VPShuf); in deinterleave8bitStride3()
561 setGroupSize(VT, GroupSize); in deinterleave8bitStride3()
611 int VF = VT.getVectorNumElements(); in group2Shuffle()
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H A DX86ISelLowering.h1016 bool isSafeMemOpType(MVT VT) const override;
1160 auto VTIsOk = [](EVT VT) -> bool { in shouldTransformSignedTruncationCheck()
1161 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || in shouldTransformSignedTruncationCheck()
1162 VT == MVT::i64; in shouldTransformSignedTruncationCheck()
1184 return VT.isScalarInteger(); in convertSetCCLogicToBitwiseLogic()
1192 EVT VT) const override;
1390 bool isFPImmLegal(const APFloat &Imm, EVT VT,
1422 bool isScalarFPTypeInSSEReg(EVT VT) const;
1448 EVT EltVT = VT.getScalarType();
1575 if (VT == MVT::f80) in getTypeToTransformTo()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp882 if (VT.isVector()) in initActions()
887 VT, Expand); in initActions()
905 VT, Expand); in initActions()
982 assert(isTypeLegal(VT)); in canOpTrap()
1008 if (VT.isSimple()) { in getTypeConversion()
1028 if (!VT.isVector()) { in getTypeConversion()
1460 if (isTypeLegal(VT)) in computeRegisterProperties()
1541 if (NVT == VT) { in computeRegisterProperties()
1629 EVT PartVT = VT; in getVectorTypeBreakdown()
1728 EVT VT = ValueVTs[j]; in GetReturnInfo() local
[all …]
H A DCallingConvLower.cpp90 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
103 MVT VT = Outs[i].VT; in CheckReturn() local
105 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeReturn()
165 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
167 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
179 if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { in AnalyzeCallResult()
194 if (VT.isVector()) in isValueTypeInRegForCC()
196 if (!VT.isInteger()) in isValueTypeInRegForCC()
[all …]
H A DLowLevelType.cpp18 LLT::LLT(MVT VT) { in LLT() argument
19 if (VT.isVector()) { in LLT()
20 bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector(); in LLT()
22 VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(), in LLT()
24 } else if (VT.isValid() && !VT.isScalableTargetExtVT()) { in LLT()
28 ElementCount::getFixed(0), VT.getSizeInBits(), /*AddressSpace=*/0); in LLT()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp70 if (VT.isInteger()) in PreprocessISelDAG()
73 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL); in PreprocessISelDAG()
86 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() && in PreprocessISelDAG()
839 assert((VT == Subtarget->getXLenVT() || VT == MVT::i32) && "Unexpected VT"); in Select()
908 switch (VT.SimpleTy) { in Select()
935 Opc, DL, VT, Imm, in Select()
1133 RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT), in Select()
1176 RISCV::SRLIW, DL, VT, X, CurDAG->getTargetConstant(C2, DL, VT)); in Select()
2006 VT = TLI.getContainerForFixedLengthVector(VT); in Select()
2318 if (!VT.isScalarInteger() && VT != MVT::f16 && VT != MVT::f32 && in isWorthFoldingAdd()
[all …]
H A DRISCVISelLowering.cpp1863 if (VT.isFixedLengthVector() && !isTypeLegal(VT)) in shouldFoldSelectWithIdentityConstant()
2707 return getLMULCost(VT) * getLMULCost(VT); in getVRGatherVVCost()
3582 VT.isFloatingPoint() ? VT.changeVectorElementTypeToInteger() : VT; in lowerBuildVectorOfConstants()
11624 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) && in ReplaceNodeResults()
13871 if (VT.isVector() && TLI.isTypeLegal(VT)) { in performFP_TO_INTCombine()
13923 if (VT != MVT::i32 && VT != XLenVT) in performFP_TO_INTCombine()
18624 MVT VT = Outs[i].VT; in CanLowerReturn() local
19180 if (VT == MVT::f32 || VT == MVT::Other) in getRegForInlineAsmConstraint()
19609 EVT VT; in getPreIndexedAddressParts() local
19632 EVT VT; in getPostIndexedAddressParts() local
[all …]
H A DRISCVISelLowering.h473 bool isFPImmLegal(const APFloat &Imm, EVT VT,
525 shouldExpandBuildVectorWithShuffles(EVT VT,
529 InstructionCost getLMULCost(MVT VT) const;
533 InstructionCost getVSlideVXCost(MVT VT) const;
534 InstructionCost getVSlideVICost(MVT VT) const;
593 EVT VT) const override;
597 if (VT == MVT::i8 || VT == MVT::i16) in shouldFormOverflowOp()
611 return VT.isScalarInteger(); in convertSetCCLogicToBitwiseLogic()
615 bool isCtpopFast(EVT VT) const override;
739 static RISCVII::VLMUL getLMUL(MVT VT);
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp152 if (VT == MVT::i64) in AMDGPUTargetLowering()
490 VT, Expand); in AMDGPUTargetLowering()
906 return VT == MVT::f32 || VT == MVT::f64 || in isFAbsFree()
913 VT = VT.getScalarType(); in isFNegFree()
914 return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16; in isFNegFree()
1901 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
2173 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2590 MVT VT = MVT::f32; in getScaledLogInput() local
3727 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT)) in shouldCombineMemoryType()
3984 if (VT != MVT::i64) in performShlCombine()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1113 if (VT != MVT::i8 && VT != MVT::i16) { in getPreIndexedAddressParts()
1170 if (VT != MVT::i8 && VT != MVT::i16) { in getPostIndexedAddressParts()
1263 MVT VT = Args[i].VT; in analyzeArguments() local
1289 MVT VT = Args[i].VT; in analyzeArguments() local
1367 MVT VT = Args[i].VT; in analyzeReturnValues() local
2663 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2679 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2696 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2701 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2706 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp209 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
1909 (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 || in getSetCCResultType()
1912 (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16))) in getSetCCResultType()
6563 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
9009 if ((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) && in LowerVECTOR_SHUFFLE()
9291 assert((VT == MVT::v16i1 || VT == MVT::v8i1 || VT == MVT::v4i1) && in LowerTruncatei1()
14409 VT == MVT::v4i1 || VT == MVT::v8i1 || VT == MVT::v16i1) in PerformANDCombine()
19785 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { in getARMIndexedAddressParts()
20433 if (VT == MVT::f32 || VT == MVT::f16 || VT == MVT::bf16) in getRegForInlineAsmConstraint()
20443 if (VT == MVT::f32 || VT == MVT::f16 || VT == MVT::bf16) in getRegForInlineAsmConstraint()
[all …]

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