Lines Matching refs:VT
62 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
64 setLoadExtAction(N, VT, MVT::i1, Promote); in AVRTargetLowering()
65 setLoadExtAction(N, VT, MVT::i8, Expand); in AVRTargetLowering()
71 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
72 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
73 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
74 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
75 setOperationAction(ISD::SUBE, VT, Legal); in AVRTargetLowering()
140 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
141 setOperationAction(ISD::ATOMIC_SWAP, VT, Expand); in AVRTargetLowering()
142 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Expand); in AVRTargetLowering()
143 setOperationAction(ISD::ATOMIC_LOAD_NAND, VT, Expand); in AVRTargetLowering()
144 setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Expand); in AVRTargetLowering()
145 setOperationAction(ISD::ATOMIC_LOAD_MIN, VT, Expand); in AVRTargetLowering()
146 setOperationAction(ISD::ATOMIC_LOAD_UMAX, VT, Expand); in AVRTargetLowering()
147 setOperationAction(ISD::ATOMIC_LOAD_UMIN, VT, Expand); in AVRTargetLowering()
183 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
184 setOperationAction(ISD::MULHS, VT, Expand); in AVRTargetLowering()
185 setOperationAction(ISD::MULHU, VT, Expand); in AVRTargetLowering()
188 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
189 setOperationAction(ISD::CTPOP, VT, Expand); in AVRTargetLowering()
190 setOperationAction(ISD::CTLZ, VT, Expand); in AVRTargetLowering()
191 setOperationAction(ISD::CTTZ, VT, Expand); in AVRTargetLowering()
194 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
195 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in AVRTargetLowering()
275 EVT VT) const { in getSetCCResultType()
276 assert(!VT.isVector() && "No AVR SetCC type for vectors!"); in getSetCCResultType()
283 EVT VT = Op.getValueType(); in LowerShifts() local
285 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) && in LowerShifts()
288 if (VT.getSizeInBits() == 32) { in LowerShifts()
344 return DAG.getNode(AVRISD::LSLLOOP, dl, VT, N->getOperand(0), in LowerShifts()
347 return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0), in LowerShifts()
353 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
354 return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt); in LowerShifts()
360 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
361 return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt); in LowerShifts()
364 return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0), in LowerShifts()
378 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
382 ShiftAmount = ShiftAmount % VT.getSizeInBits(); in LowerShifts()
395 if (VT.getSizeInBits() == 8) { in LowerShifts()
398 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
400 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0xf0, dl, VT)); in LowerShifts()
405 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
407 DAG.getNode(ISD::AND, dl, VT, Victim, DAG.getConstant(0x0f, dl, VT)); in LowerShifts()
411 Victim = DAG.getNode(AVRISD::LSLBN, dl, VT, Victim, in LowerShifts()
412 DAG.getConstant(7, dl, VT)); in LowerShifts()
416 Victim = DAG.getNode(AVRISD::LSRBN, dl, VT, Victim, in LowerShifts()
417 DAG.getConstant(7, dl, VT)); in LowerShifts()
421 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, in LowerShifts()
422 DAG.getConstant(6, dl, VT)); in LowerShifts()
426 Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim, in LowerShifts()
427 DAG.getConstant(7, dl, VT)); in LowerShifts()
431 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
433 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
437 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
439 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
444 DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
449 DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT)); in LowerShifts()
454 Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim); in LowerShifts()
457 } else if (VT.getSizeInBits() == 16) { in LowerShifts()
462 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
463 DAG.getConstant(15, dl, VT)); in LowerShifts()
467 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
468 DAG.getConstant(14, dl, VT)); in LowerShifts()
472 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
473 DAG.getConstant(7, dl, VT)); in LowerShifts()
482 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
483 DAG.getConstant(4, dl, VT)); in LowerShifts()
487 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
488 DAG.getConstant(4, dl, VT)); in LowerShifts()
497 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
498 DAG.getConstant(8, dl, VT)); in LowerShifts()
504 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
505 DAG.getConstant(8, dl, VT)); in LowerShifts()
511 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
512 DAG.getConstant(8, dl, VT)); in LowerShifts()
523 Victim = DAG.getNode(AVRISD::LSLWN, dl, VT, Victim, in LowerShifts()
524 DAG.getConstant(12, dl, VT)); in LowerShifts()
530 Victim = DAG.getNode(AVRISD::LSRWN, dl, VT, Victim, in LowerShifts()
531 DAG.getConstant(12, dl, VT)); in LowerShifts()
537 Victim = DAG.getNode(AVRISD::ASRWN, dl, VT, Victim, in LowerShifts()
538 DAG.getConstant(8, dl, VT)); in LowerShifts()
549 Victim = DAG.getNode(Opc8, dl, VT, Victim); in LowerShifts()
560 EVT VT = Op->getValueType(0); in LowerDivRem() local
561 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); in LowerDivRem()
564 switch (VT.getSimpleVT().SimpleTy) { in LowerDivRem()
712 EVT VT = LHS.getValueType(); in getAVRCmp() local
738 LHS = DAG.getConstant(0, DL, VT); in getAVRCmp()
745 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); in getAVRCmp()
764 LHS = DAG.getConstant(0, DL, VT); in getAVRCmp()
789 RHS = DAG.getConstant(C->getSExtValue() + 1, DL, VT); in getAVRCmp()
802 if (VT == MVT::i32) { in getAVRCmp()
821 } else if (VT == MVT::i64) { in getAVRCmp()
861 } else if (VT == MVT::i8 || VT == MVT::i16) { in getAVRCmp()
865 (VT == MVT::i8) in getAVRCmp()
1091 EVT VT; in getPreIndexedAddressParts() local
1096 VT = LD->getMemoryVT(); in getPreIndexedAddressParts()
1104 VT = ST->getMemoryVT(); in getPreIndexedAddressParts()
1113 if (VT != MVT::i8 && VT != MVT::i16) { in getPreIndexedAddressParts()
1126 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) { in getPreIndexedAddressParts()
1148 EVT VT; in getPostIndexedAddressParts() local
1152 VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
1156 VT = ST->getMemoryVT(); in getPostIndexedAddressParts()
1164 if (VT == MVT::i16 && !Subtarget.hasLowByteFirst()) in getPostIndexedAddressParts()
1170 if (VT != MVT::i8 && VT != MVT::i16) { in getPostIndexedAddressParts()
1182 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) { in getPostIndexedAddressParts()
1263 MVT VT = Args[i].VT; in analyzeArguments() local
1269 unsigned TotalBytes = VT.getStoreSize(); in analyzeArguments()
1274 TotalBytes += Args[j].VT.getStoreSize(); in analyzeArguments()
1289 MVT VT = Args[i].VT; in analyzeArguments() local
1292 auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext()); in analyzeArguments()
1296 CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full)); in analyzeArguments()
1299 if (VT == MVT::i8) { in analyzeArguments()
1301 } else if (VT == MVT::i16) { in analyzeArguments()
1308 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); in analyzeArguments()
1311 RegIdx -= VT.getStoreSize(); in analyzeArguments()
1324 TotalBytes += Arg.VT.getStoreSize(); in getTotalArgumentsSizeInBytes()
1367 MVT VT = Args[i].VT; in analyzeReturnValues() local
1369 if (VT == MVT::i8) { in analyzeReturnValues()
1371 } else if (VT == MVT::i16) { in analyzeReturnValues()
1377 CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full)); in analyzeReturnValues()
1379 RegIdx -= VT.getStoreSize(); in analyzeReturnValues()
2653 MVT VT) const { in getRegForInlineAsmConstraint()
2657 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2659 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
2663 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2667 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2669 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
2673 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2675 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
2679 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2685 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2687 else if (VT == MVT::i16) in getRegForInlineAsmConstraint()
2691 if (VT == MVT::i8) in getRegForInlineAsmConstraint()
2696 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2701 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2706 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2711 if (VT == MVT::i8 || VT == MVT::i16) in getRegForInlineAsmConstraint()
2720 Subtarget.getRegisterInfo(), Constraint, VT); in getRegForInlineAsmConstraint()
2830 Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT, in getRegisterByName() argument
2834 if (VT == LLT::scalar(8)) { in getRegisterByName()