Lines Matching refs:VT
40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
41 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
147 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
148 setLoadExtAction({ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, MVT::i64, VT, in AMDGPUTargetLowering()
151 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
152 if (VT == MVT::i64) in AMDGPUTargetLowering()
156 setLoadExtAction(Op, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
157 setLoadExtAction(Op, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
158 setLoadExtAction(Op, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
159 setLoadExtAction(Op, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
163 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AMDGPUTargetLowering() local
166 setLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}, VT, MemVT, in AMDGPUTargetLowering()
410 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
412 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, VT, in AMDGPUTargetLowering()
416 setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom); in AMDGPUTargetLowering()
419 setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, VT, Expand); in AMDGPUTargetLowering()
421 setOperationAction({ISD::BSWAP, ISD::CTTZ, ISD::CTLZ}, VT, Expand); in AMDGPUTargetLowering()
424 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
449 for (auto VT : {MVT::i8, MVT::i16}) in AMDGPUTargetLowering()
450 setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom); in AMDGPUTargetLowering()
456 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
470 VT, Expand); in AMDGPUTargetLowering()
477 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
490 VT, Expand); in AMDGPUTargetLowering()
657 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) { in opMustUseVOP3Encoding() argument
659 VT == MVT::f64; in opMustUseVOP3Encoding()
718 MVT VT = N->getValueType(0).getScalarType().getSimpleVT(); in allUsesHaveSourceMods() local
727 if (!opMustUseVOP3Encoding(U, VT)) { in allUsesHaveSourceMods()
736 EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, in getTypeForExtReturn() argument
738 assert(!VT.isVector() && "only scalar expected"); in getTypeForExtReturn()
741 unsigned Size = VT.getSizeInBits(); in getTypeForExtReturn()
757 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, in isFPImmLegal() argument
759 EVT ScalarVT = VT.getScalarType(); in isFPImmLegal()
765 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
766 EVT ScalarVT = VT.getScalarType(); in ShouldShrinkFPConstant()
881 EVT VT = Op.getValueType(); in getNegatedExpression() local
887 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
902 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const { in isFAbsFree()
903 assert(VT.isFloatingPoint()); in isFAbsFree()
906 return VT == MVT::f32 || VT == MVT::f64 || in isFAbsFree()
907 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()
910 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const { in isFNegFree()
911 assert(VT.isFloatingPoint()); in isFNegFree()
913 VT = VT.getScalarType(); in isFNegFree()
914 return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f16; in isFNegFree()
1305 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT)); in lowerUnhandledCall()
1471 EVT VT = Op.getValueType(); in LowerCONCAT_VECTORS() local
1472 if (VT.getVectorElementType().getSizeInBits() < 32) { in LowerCONCAT_VECTORS()
1491 return DAG.getNode(ISD::BITCAST, SL, VT, BV); in LowerCONCAT_VECTORS()
1506 EVT VT = Op.getValueType(); in LowerEXTRACT_SUBVECTOR() local
1509 if (VT.getScalarSizeInBits() == 16 && Start % 2 == 0) { in LowerEXTRACT_SUBVECTOR()
1510 unsigned NumElt = VT.getVectorNumElements(); in LowerEXTRACT_SUBVECTOR()
1527 return DAG.getNode(ISD::BITCAST, SL, VT, Tmp); in LowerEXTRACT_SUBVECTOR()
1531 VT.getVectorNumElements()); in LowerEXTRACT_SUBVECTOR()
1555 const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, in combineFMinMaxLegacyImpl() argument
1576 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1577 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1595 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1596 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1601 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1602 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1613 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS); in combineFMinMaxLegacyImpl()
1614 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS); in combineFMinMaxLegacyImpl()
1623 SDValue AMDGPUTargetLowering::combineFMinMaxLegacy(const SDLoc &DL, EVT VT, in combineFMinMaxLegacy() argument
1629 return combineFMinMaxLegacyImpl(DL, VT, LHS, RHS, True, False, CC, DCI); in combineFMinMaxLegacy()
1651 combineFMinMaxLegacyImpl(DL, VT, LHS, RHS, NegTrue, False, CC, DCI); in combineFMinMaxLegacy()
1653 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineFMinMaxLegacy()
1696 AMDGPUTargetLowering::getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const { in getSplitDestVTs() argument
1698 EVT EltVT = VT.getVectorElementType(); in getSplitDestVTs()
1699 unsigned NumElts = VT.getVectorNumElements(); in getSplitDestVTs()
1729 EVT VT = Op.getValueType(); in SplitVectorLoad() local
1735 if (VT.getVectorNumElements() == 2) { in SplitVectorLoad()
1750 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG); in SplitVectorLoad()
1770 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad); in SplitVectorLoad()
1772 Join = DAG.getNode(ISD::INSERT_SUBVECTOR, SL, VT, DAG.getUNDEF(VT), LoLoad, in SplitVectorLoad()
1776 VT, Join, HiLoad, in SplitVectorLoad()
1789 EVT VT = Op.getValueType(); in WidenOrSplitVectorLoad() local
1807 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4); in WidenOrSplitVectorLoad()
1814 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
1824 EVT VT = Val.getValueType(); in SplitVectorStore() local
1828 if (VT.getVectorNumElements() == 2) in SplitVectorStore()
1840 std::tie(LoVT, HiVT) = getSplitDestVTs(VT, DAG); in SplitVectorStore()
1867 EVT VT = Op.getValueType(); in LowerDIVREM24() local
1881 unsigned BitSize = VT.getSizeInBits(); in LowerDIVREM24()
1894 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS); in LowerDIVREM24()
1897 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
1898 DAG.getConstant(BitSize - 2, DL, VT)); in LowerDIVREM24()
1901 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT)); in LowerDIVREM24()
1949 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in LowerDIVREM24()
1955 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT)); in LowerDIVREM24()
1958 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24()
1961 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
1962 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); in LowerDIVREM24()
1968 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
1969 Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize); in LowerDIVREM24()
1971 SDValue TruncMask = DAG.getConstant((UINT64_C(1) << DivBits) - 1, DL, VT); in LowerDIVREM24()
1972 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
1973 Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask); in LowerDIVREM24()
1983 EVT VT = Op.getValueType(); in LowerUDIVREM64() local
1985 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64"); in LowerUDIVREM64()
1987 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerUDIVREM64()
2045 SDValue Rcp64 = DAG.getBitcast(VT, in LowerUDIVREM64()
2048 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64()
2049 SDValue One64 = DAG.getConstant(1, DL, VT); in LowerUDIVREM64()
2054 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
2055 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64); in LowerUDIVREM64()
2056 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
2064 SDValue Add1 = DAG.getBitcast(VT, in LowerUDIVREM64()
2068 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); in LowerUDIVREM64()
2069 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
2077 SDValue Add2 = DAG.getBitcast(VT, in LowerUDIVREM64()
2080 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2082 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3); in LowerUDIVREM64()
2091 SDValue Sub1 = DAG.getBitcast(VT, in LowerUDIVREM64()
2112 SDValue Sub2 = DAG.getBitcast(VT, in LowerUDIVREM64()
2115 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); in LowerUDIVREM64()
2124 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); in LowerUDIVREM64()
2132 SDValue Sub3 = DAG.getBitcast(VT, in LowerUDIVREM64()
2170 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); in LowerUDIVREM64()
2173 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); in LowerUDIVREM64()
2175 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); in LowerUDIVREM64()
2183 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); in LowerUDIVREM64()
2196 EVT VT = Op.getValueType(); in LowerUDIVREM() local
2198 if (VT == MVT::i64) { in LowerUDIVREM()
2204 if (VT == MVT::i32) { in LowerUDIVREM()
2216 SDValue Z = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Y); in LowerUDIVREM()
2219 SDValue NegY = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Y); in LowerUDIVREM()
2220 SDValue NegYZ = DAG.getNode(ISD::MUL, DL, VT, NegY, Z); in LowerUDIVREM()
2221 Z = DAG.getNode(ISD::ADD, DL, VT, Z, in LowerUDIVREM()
2222 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2225 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
2227 DAG.getNode(ISD::SUB, DL, VT, X, DAG.getNode(ISD::MUL, DL, VT, Q, Y)); in LowerUDIVREM()
2230 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in LowerUDIVREM()
2231 SDValue One = DAG.getConstant(1, DL, VT); in LowerUDIVREM()
2233 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2234 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2235 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2236 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2240 Q = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2241 DAG.getNode(ISD::ADD, DL, VT, Q, One), Q); in LowerUDIVREM()
2242 R = DAG.getNode(ISD::SELECT, DL, VT, Cond, in LowerUDIVREM()
2243 DAG.getNode(ISD::SUB, DL, VT, R, Y), R); in LowerUDIVREM()
2251 EVT VT = Op.getValueType(); in LowerSDIVREM() local
2256 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSDIVREM()
2257 SDValue NegOne = DAG.getConstant(-1, DL, VT); in LowerSDIVREM()
2259 if (VT == MVT::i32) { in LowerSDIVREM()
2264 if (VT == MVT::i64 && in LowerSDIVREM()
2267 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); in LowerSDIVREM()
2275 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)), in LowerSDIVREM()
2276 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1)) in LowerSDIVREM()
2283 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign); in LowerSDIVREM()
2286 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign); in LowerSDIVREM()
2287 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign); in LowerSDIVREM()
2289 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign); in LowerSDIVREM()
2290 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign); in LowerSDIVREM()
2292 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM()
2295 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
2296 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign); in LowerSDIVREM()
2298 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); in LowerSDIVREM()
2299 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign); in LowerSDIVREM()
2311 EVT VT = Op.getValueType(); in LowerFREM() local
2316 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y, Flags); in LowerFREM()
2317 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2318 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2320 return DAG.getNode(ISD::FMA, SL, VT, Neg, Y, X, Flags); in LowerFREM()
2447 auto VT = Op.getValueType(); in LowerFRINT() local
2449 return DAG.getNode(ISD::FROUNDEVEN, SDLoc(Op), VT, Arg); in LowerFRINT()
2460 EVT VT = Op.getValueType(); in LowerFROUND() local
2462 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2466 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T); in LowerFROUND()
2468 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff); in LowerFROUND()
2470 const SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFROUND()
2471 const SDValue One = DAG.getConstantFP(1.0, SL, VT); in LowerFROUND()
2474 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in LowerFROUND()
2476 const SDValue Half = DAG.getConstantFP(0.5, SL, VT); in LowerFROUND()
2478 SDValue OneOrZeroFP = DAG.getNode(ISD::SELECT, SL, VT, Cmp, One, Zero); in LowerFROUND()
2480 SDValue SignedOffset = DAG.getNode(ISD::FCOPYSIGN, SL, VT, OneOrZeroFP, X); in LowerFROUND()
2481 return DAG.getNode(ISD::FADD, SL, VT, T, SignedOffset); in LowerFROUND()
2554 EVT VT = Src.getValueType(); in getIsLtSmallestNormal() local
2555 const fltSemantics &Semantics = SelectionDAG::EVTToAPFloatSemantics(VT); in getIsLtSmallestNormal()
2557 DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT); in getIsLtSmallestNormal()
2562 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src, in getIsLtSmallestNormal()
2571 EVT VT = Src.getValueType(); in getIsFinite() local
2572 const fltSemantics &Semantics = SelectionDAG::EVTToAPFloatSemantics(VT); in getIsFinite()
2573 SDValue Inf = DAG.getConstantFP(APFloat::getInf(Semantics), SL, VT); in getIsFinite()
2575 SDValue Fabs = DAG.getNode(ISD::FABS, SL, VT, Src, Flags); in getIsFinite()
2577 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Fabs, in getIsFinite()
2590 MVT VT = MVT::f32; in getScaledLogInput() local
2593 DAG.getConstantFP(APFloat::getSmallestNormalized(Semantics), SL, VT); in getScaledLogInput()
2596 SL, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Src, in getScaledLogInput()
2599 SDValue Scale32 = DAG.getConstantFP(0x1.0p+32, SL, VT); in getScaledLogInput()
2600 SDValue One = DAG.getConstantFP(1.0, SL, VT); in getScaledLogInput()
2602 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, Scale32, One, Flags); in getScaledLogInput()
2604 SDValue ScaledInput = DAG.getNode(ISD::FMUL, SL, VT, Src, ScaleFactor, Flags); in getScaledLogInput()
2616 EVT VT = Op.getValueType(); in LowerFLOG2() local
2620 if (VT == MVT::f16) { in LowerFLOG2()
2625 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in LowerFLOG2()
2632 return DAG.getNode(AMDGPUISD::LOG, SL, VT, Src, Flags); in LowerFLOG2()
2634 SDValue Log2 = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOG2()
2636 SDValue ThirtyTwo = DAG.getConstantFP(32.0, SL, VT); in LowerFLOG2()
2637 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in LowerFLOG2()
2639 DAG.getNode(ISD::SELECT, SL, VT, IsLtSmallestNormal, ThirtyTwo, Zero); in LowerFLOG2()
2640 return DAG.getNode(ISD::FSUB, SL, VT, Log2, ResultOffset, Flags); in LowerFLOG2()
2643 static SDValue getMad(SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue X, in getMad() argument
2645 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Y, Flags); in getMad()
2646 return DAG.getNode(ISD::FADD, SL, VT, Mul, C, Flags); in getMad()
2652 EVT VT = Op.getValueType(); in LowerFLOGCommon() local
2660 if (VT == MVT::f16 || Flags.hasApproximateFuncs() || in LowerFLOGCommon()
2663 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()
2669 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()
2670 return DAG.getNode(ISD::FP_ROUND, DL, VT, Lowered, in LowerFLOGCommon()
2681 SDValue Y = DAG.getNode(AMDGPUISD::LOG, DL, VT, X, Flags); in LowerFLOGCommon()
2693 SDValue C = DAG.getConstantFP(IsLog10 ? c_log10 : c_log, DL, VT); in LowerFLOGCommon()
2694 SDValue CC = DAG.getConstantFP(IsLog10 ? cc_log10 : cc_log, DL, VT); in LowerFLOGCommon()
2696 R = DAG.getNode(ISD::FMUL, DL, VT, Y, C, Flags); in LowerFLOGCommon()
2697 SDValue NegR = DAG.getNode(ISD::FNEG, DL, VT, R, Flags); in LowerFLOGCommon()
2698 SDValue FMA0 = DAG.getNode(ISD::FMA, DL, VT, Y, C, NegR, Flags); in LowerFLOGCommon()
2699 SDValue FMA1 = DAG.getNode(ISD::FMA, DL, VT, Y, CC, FMA0, Flags); in LowerFLOGCommon()
2700 R = DAG.getNode(ISD::FADD, DL, VT, R, FMA1, Flags); in LowerFLOGCommon()
2710 SDValue CH = DAG.getConstantFP(IsLog10 ? ch_log10 : ch_log, DL, VT); in LowerFLOGCommon()
2711 SDValue CT = DAG.getConstantFP(IsLog10 ? ct_log10 : ct_log, DL, VT); in LowerFLOGCommon()
2717 SDValue YT = DAG.getNode(ISD::FSUB, DL, VT, Y, YH, Flags); in LowerFLOGCommon()
2719 SDValue YTCT = DAG.getNode(ISD::FMUL, DL, VT, YT, CT, Flags); in LowerFLOGCommon()
2720 SDValue Mad0 = getMad(DAG, DL, VT, YH, CT, YTCT, Flags); in LowerFLOGCommon()
2721 SDValue Mad1 = getMad(DAG, DL, VT, YT, CH, Mad0, Flags); in LowerFLOGCommon()
2722 R = getMad(DAG, DL, VT, YH, CH, Mad1); in LowerFLOGCommon()
2731 R = DAG.getNode(ISD::SELECT, DL, VT, IsFinite, R, Y, Flags); in LowerFLOGCommon()
2735 SDValue Zero = DAG.getConstantFP(0.0f, DL, VT); in LowerFLOGCommon()
2737 DAG.getConstantFP(IsLog10 ? 0x1.344136p+3f : 0x1.62e430p+4f, DL, VT); in LowerFLOGCommon()
2739 DAG.getNode(ISD::SELECT, DL, VT, IsScaled, ShiftK, Zero, Flags); in LowerFLOGCommon()
2740 R = DAG.getNode(ISD::FSUB, DL, VT, R, Shift, Flags); in LowerFLOGCommon()
2755 EVT VT = Src.getValueType(); in LowerFLOGUnsafe() local
2757 VT == MVT::f32 ? (unsigned)AMDGPUISD::LOG : (unsigned)ISD::FLOG2; in LowerFLOGUnsafe()
2762 if (VT == MVT::f32) { in LowerFLOGUnsafe()
2765 SDValue LogSrc = DAG.getNode(AMDGPUISD::LOG, SL, VT, ScaledInput, Flags); in LowerFLOGUnsafe()
2767 DAG.getConstantFP(-32.0 * Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2769 SDValue Zero = DAG.getConstantFP(0.0f, SL, VT); in LowerFLOGUnsafe()
2771 SDValue ResultOffset = DAG.getNode(ISD::SELECT, SL, VT, IsScaled, in LowerFLOGUnsafe()
2774 SDValue Log2Inv = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2777 return DAG.getNode(ISD::FMA, SL, VT, LogSrc, Log2Inv, ResultOffset, in LowerFLOGUnsafe()
2779 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, LogSrc, Log2Inv, Flags); in LowerFLOGUnsafe()
2780 return DAG.getNode(ISD::FADD, SL, VT, Mul, ResultOffset); in LowerFLOGUnsafe()
2784 SDValue Log2Operand = DAG.getNode(LogOp, SL, VT, Src, Flags); in LowerFLOGUnsafe()
2785 SDValue Log2BaseInvertedOperand = DAG.getConstantFP(Log2BaseInverted, SL, VT); in LowerFLOGUnsafe()
2787 return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand, in LowerFLOGUnsafe()
2796 EVT VT = Op.getValueType(); in lowerFEXP2() local
2800 if (VT == MVT::f16) { in lowerFEXP2()
2805 return DAG.getNode(ISD::FP_ROUND, SL, VT, Log, in lowerFEXP2()
2809 assert(VT == MVT::f32); in lowerFEXP2()
2818 SDValue RangeCheckConst = DAG.getConstantFP(-0x1.f80000p+6f, SL, VT); in lowerFEXP2()
2820 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in lowerFEXP2()
2825 SDValue SixtyFour = DAG.getConstantFP(0x1.0p+6f, SL, VT); in lowerFEXP2()
2826 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in lowerFEXP2()
2829 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, SixtyFour, Zero); in lowerFEXP2()
2831 SDValue AddInput = DAG.getNode(ISD::FADD, SL, VT, Src, AddOffset, Flags); in lowerFEXP2()
2832 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, AddInput, Flags); in lowerFEXP2()
2834 SDValue TwoExpNeg64 = DAG.getConstantFP(0x1.0p-64f, SL, VT); in lowerFEXP2()
2835 SDValue One = DAG.getConstantFP(1.0, SL, VT); in lowerFEXP2()
2837 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One); in lowerFEXP2()
2839 return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags); in lowerFEXP2()
2845 EVT VT = X.getValueType(); in lowerFEXPUnsafe() local
2846 const SDValue Log2E = DAG.getConstantFP(numbers::log2e, SL, VT); in lowerFEXPUnsafe()
2848 if (VT != MVT::f32 || !needsDenormHandlingF32(DAG, X, Flags)) { in lowerFEXPUnsafe()
2850 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Log2E, Flags); in lowerFEXPUnsafe()
2851 return DAG.getNode(VT == MVT::f32 ? (unsigned)AMDGPUISD::EXP in lowerFEXPUnsafe()
2853 SL, VT, Mul, Flags); in lowerFEXPUnsafe()
2856 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in lowerFEXPUnsafe()
2858 SDValue Threshold = DAG.getConstantFP(-0x1.5d58a0p+6f, SL, VT); in lowerFEXPUnsafe()
2861 SDValue ScaleOffset = DAG.getConstantFP(0x1.0p+6f, SL, VT); in lowerFEXPUnsafe()
2863 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXPUnsafe()
2866 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXPUnsafe()
2868 SDValue ExpInput = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, Log2E, Flags); in lowerFEXPUnsafe()
2870 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, ExpInput, Flags); in lowerFEXPUnsafe()
2872 SDValue ResultScaleFactor = DAG.getConstantFP(0x1.969d48p-93f, SL, VT); in lowerFEXPUnsafe()
2874 DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScaleFactor, Flags); in lowerFEXPUnsafe()
2876 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, Exp2, in lowerFEXPUnsafe()
2885 const EVT VT = X.getValueType(); in lowerFEXP10Unsafe() local
2886 const unsigned Exp2Op = VT == MVT::f32 ? AMDGPUISD::EXP : ISD::FEXP2; in lowerFEXP10Unsafe()
2888 if (VT != MVT::f32 || !needsDenormHandlingF32(DAG, X, Flags)) { in lowerFEXP10Unsafe()
2890 SDValue K0 = DAG.getConstantFP(0x1.a92000p+1f, SL, VT); in lowerFEXP10Unsafe()
2891 SDValue K1 = DAG.getConstantFP(0x1.4f0978p-11f, SL, VT); in lowerFEXP10Unsafe()
2893 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, X, K0, Flags); in lowerFEXP10Unsafe()
2894 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2895 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, X, K1, Flags); in lowerFEXP10Unsafe()
2896 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2897 return DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1); in lowerFEXP10Unsafe()
2906 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in lowerFEXP10Unsafe()
2908 SDValue Threshold = DAG.getConstantFP(-0x1.2f7030p+5f, SL, VT); in lowerFEXP10Unsafe()
2911 SDValue ScaleOffset = DAG.getConstantFP(0x1.0p+5f, SL, VT); in lowerFEXP10Unsafe()
2912 SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags); in lowerFEXP10Unsafe()
2914 DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X); in lowerFEXP10Unsafe()
2916 SDValue K0 = DAG.getConstantFP(0x1.a92000p+1f, SL, VT); in lowerFEXP10Unsafe()
2917 SDValue K1 = DAG.getConstantFP(0x1.4f0978p-11f, SL, VT); in lowerFEXP10Unsafe()
2919 SDValue Mul0 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K0, Flags); in lowerFEXP10Unsafe()
2920 SDValue Exp2_0 = DAG.getNode(Exp2Op, SL, VT, Mul0, Flags); in lowerFEXP10Unsafe()
2921 SDValue Mul1 = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, K1, Flags); in lowerFEXP10Unsafe()
2922 SDValue Exp2_1 = DAG.getNode(Exp2Op, SL, VT, Mul1, Flags); in lowerFEXP10Unsafe()
2924 SDValue MulExps = DAG.getNode(ISD::FMUL, SL, VT, Exp2_0, Exp2_1, Flags); in lowerFEXP10Unsafe()
2926 SDValue ResultScaleFactor = DAG.getConstantFP(0x1.9f623ep-107f, SL, VT); in lowerFEXP10Unsafe()
2928 DAG.getNode(ISD::FMUL, SL, VT, MulExps, ResultScaleFactor, Flags); in lowerFEXP10Unsafe()
2930 return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, MulExps, in lowerFEXP10Unsafe()
2935 EVT VT = Op.getValueType(); in lowerFEXP() local
2941 if (VT.getScalarType() == MVT::f16) { in lowerFEXP()
2946 if (VT.isVector()) in lowerFEXP()
2955 return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, in lowerFEXP()
2959 assert(VT == MVT::f32); in lowerFEXP()
3002 SDValue C = DAG.getConstantFP(IsExp10 ? c_exp10 : c_exp, SL, VT); in lowerFEXP()
3003 SDValue CC = DAG.getConstantFP(IsExp10 ? cc_exp10 : cc_exp, SL, VT); in lowerFEXP()
3005 PH = DAG.getNode(ISD::FMUL, SL, VT, X, C, Flags); in lowerFEXP()
3006 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
3007 SDValue FMA0 = DAG.getNode(ISD::FMA, SL, VT, X, C, NegPH, Flags); in lowerFEXP()
3008 PL = DAG.getNode(ISD::FMA, SL, VT, X, CC, FMA0, Flags); in lowerFEXP()
3016 SDValue CH = DAG.getConstantFP(IsExp10 ? ch_exp10 : ch_exp, SL, VT); in lowerFEXP()
3017 SDValue CL = DAG.getConstantFP(IsExp10 ? cl_exp10 : cl_exp, SL, VT); in lowerFEXP()
3022 SDValue XH = DAG.getNode(ISD::BITCAST, SL, VT, XHAsInt); in lowerFEXP()
3023 SDValue XL = DAG.getNode(ISD::FSUB, SL, VT, X, XH, Flags); in lowerFEXP()
3025 PH = DAG.getNode(ISD::FMUL, SL, VT, XH, CH, Flags); in lowerFEXP()
3027 SDValue XLCL = DAG.getNode(ISD::FMUL, SL, VT, XL, CL, Flags); in lowerFEXP()
3028 SDValue Mad0 = getMad(DAG, SL, VT, XL, CH, XLCL, Flags); in lowerFEXP()
3029 PL = getMad(DAG, SL, VT, XH, CL, Mad0, Flags); in lowerFEXP()
3032 SDValue E = DAG.getNode(ISD::FROUNDEVEN, SL, VT, PH, Flags); in lowerFEXP()
3035 SDValue PHSubE = DAG.getNode(ISD::FSUB, SL, VT, PH, E, FlagsNoContract); in lowerFEXP()
3037 SDValue A = DAG.getNode(ISD::FADD, SL, VT, PHSubE, PL, Flags); in lowerFEXP()
3039 SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, A, Flags); in lowerFEXP()
3041 SDValue R = DAG.getNode(ISD::FLDEXP, SL, VT, Exp2, IntE, Flags); in lowerFEXP()
3044 DAG.getConstantFP(IsExp10 ? -0x1.66d3e8p+5f : -0x1.9d1da0p+6f, SL, VT); in lowerFEXP()
3046 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in lowerFEXP()
3047 SDValue Zero = DAG.getConstantFP(0.0, SL, VT); in lowerFEXP()
3051 R = DAG.getNode(ISD::SELECT, SL, VT, Underflow, Zero, R); in lowerFEXP()
3056 DAG.getConstantFP(IsExp10 ? 0x1.344136p+5f : 0x1.62e430p+6f, SL, VT); in lowerFEXP()
3060 DAG.getConstantFP(APFloat::getInf(APFloat::IEEEsingle()), SL, VT); in lowerFEXP()
3061 R = DAG.getNode(ISD::SELECT, SL, VT, Overflow, Inf, R); in lowerFEXP()
3616 MVT VT = Op.getSimpleValueType(); in LowerSIGN_EXTEND_INREG() local
3617 MVT ScalarVT = VT.getScalarType(); in LowerSIGN_EXTEND_INREG()
3619 assert(VT.isVector()); in LowerSIGN_EXTEND_INREG()
3625 unsigned NElts = VT.getVectorNumElements(); in LowerSIGN_EXTEND_INREG()
3633 return DAG.getBuildVector(VT, DL, Args); in LowerSIGN_EXTEND_INREG()
3645 EVT VT = Op.getValueType(); in isI24() local
3646 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated in isI24()
3725 bool AMDGPUTargetLowering::shouldCombineMemoryType(EVT VT) const { in shouldCombineMemoryType()
3727 if (VT.getScalarType() == MVT::i32 || isTypeLegal(VT)) in shouldCombineMemoryType()
3730 if (!VT.isByteSized()) in shouldCombineMemoryType()
3733 unsigned Size = VT.getStoreSize(); in shouldCombineMemoryType()
3735 if ((Size == 1 || Size == 2 || Size == 4) && !VT.isVector()) in shouldCombineMemoryType()
3757 EVT VT = LN->getMemoryVT(); in performLoadCombine() local
3759 unsigned Size = VT.getStoreSize(); in performLoadCombine()
3761 if (Alignment < Size && isTypeLegal(VT)) { in performLoadCombine()
3769 VT, AS, Alignment, LN->getMemOperand()->getFlags(), &IsFast)) { in performLoadCombine()
3770 if (VT.isVector()) in performLoadCombine()
3783 if (!shouldCombineMemoryType(VT)) in performLoadCombine()
3786 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine()
3792 SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad); in performLoadCombine()
3808 EVT VT = SN->getMemoryVT(); in performStoreCombine() local
3809 unsigned Size = VT.getStoreSize(); in performStoreCombine()
3814 if (Alignment < Size && isTypeLegal(VT)) { in performStoreCombine()
3823 VT, AS, Alignment, SN->getMemOperand()->getFlags(), &IsFast)) { in performStoreCombine()
3824 if (VT.isVector()) in performStoreCombine()
3834 if (!shouldCombineMemoryType(VT)) in performStoreCombine()
3837 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine()
3845 SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal); in performStoreCombine()
3940 EVT VT = N->getValueType(0); in performShlCombine() local
3962 if (VT == MVT::i32 && RHSVal == 16 && X.getValueType() == MVT::i16 && in performShlCombine()
3972 if (VT != MVT::i64) in performShlCombine()
3980 return DAG.getZExtOrTrunc(Shl, SL, VT); in performShlCombine()
3984 if (VT != MVT::i64) in performShlCombine()
4047 EVT VT = N->getValueType(0); in performSrlCombine() local
4061 ISD::AND, SL, VT, in performSrlCombine()
4062 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)), in performSrlCombine()
4063 DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1))); in performSrlCombine()
4068 if (VT != MVT::i64) in performSrlCombine()
4093 EVT VT = N->getValueType(0); in performTruncateCombine() local
4097 if (Src.getOpcode() == ISD::BITCAST && !VT.isVector()) { in performTruncateCombine()
4102 if (VT.getFixedSizeInBits() <= EltVT.getFixedSizeInBits()) { in performTruncateCombine()
4108 return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0); in performTruncateCombine()
4116 if (Src.getOpcode() == ISD::SRL && !VT.isVector()) { in performTruncateCombine()
4129 return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt); in performTruncateCombine()
4139 if (VT.getScalarSizeInBits() < 32) { in performTruncateCombine()
4153 (Src.getOpcode() == ISD::SHL) ? 31 : (32 - VT.getScalarSizeInBits()); in performTruncateCombine()
4155 EVT MidVT = VT.isVector() ? in performTruncateCombine()
4157 VT.getVectorNumElements()) : MVT::i32; in performTruncateCombine()
4171 return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift); in performTruncateCombine()
4210 EVT VT = N->getValueType(0); in performMulCombine() local
4219 unsigned Size = VT.getSizeInBits(); in performMulCombine()
4220 if (VT.isVector() || Size > 64) in performMulCombine()
4249 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N1, MulOper); in performMulCombine()
4250 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N1); in performMulCombine()
4254 SDValue MulVal = DAG.getNode(N->getOpcode(), DL, VT, N0, MulOper); in performMulCombine()
4255 return DAG.getNode(ISD::ADD, DL, VT, MulVal, N0); in performMulCombine()
4263 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()
4292 return DAG.getSExtOrTrunc(Mul, DL, VT); in performMulCombine()
4341 EVT VT = N->getValueType(0); in performMulhsCombine() local
4343 if (!Subtarget->hasMulI24() || VT.isVector()) in performMulhsCombine()
4369 return DAG.getSExtOrTrunc(Mulhi, DL, VT); in performMulhsCombine()
4374 EVT VT = N->getValueType(0); in performMulhuCombine() local
4376 if (!Subtarget->hasMulU24() || VT.isVector() || VT.getSizeInBits() > 32) in performMulhuCombine()
4402 return DAG.getZExtOrTrunc(Mulhi, DL, VT); in performMulhuCombine()
4409 EVT VT = Op.getValueType(); in getFFBX_U32() local
4410 EVT LegalVT = getTypeToTransformTo(*DAG.getContext(), VT); in getFFBX_U32()
4415 if (VT != MVT::i32) in getFFBX_U32()
4419 if (VT != MVT::i32) in getFFBX_U32()
4420 FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX); in getFFBX_U32()
4473 EVT VT = N1.getValueType(); in distributeOpThroughSelect() local
4475 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond, in distributeOpThroughSelect()
4478 return DAG.getNode(Op, SL, VT, NewSelect); in distributeOpThroughSelect()
4496 EVT VT = N.getValueType(); in foldFreeOpFromSelect() local
4551 NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in foldFreeOpFromSelect()
4556 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, in foldFreeOpFromSelect()
4559 return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect); in foldFreeOpFromSelect()
4575 EVT VT = N->getValueType(0); in performSelectCombine() local
4596 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True); in performSelectCombine()
4599 if (VT == MVT::f32 && Subtarget->hasFminFmaxLegacy()) { in performSelectCombine()
4601 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI); in performSelectCombine()
4695 EVT VT = N->getValueType(0); in performFNegCombine() local
4713 LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4718 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4722 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4726 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4741 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4743 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags()); in performFNegCombine()
4747 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4766 MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS); in performFNegCombine()
4769 RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4773 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS); in performFNegCombine()
4777 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4801 SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS); in performFNegCombine()
4802 SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in performFNegCombine()
4805 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags()); in performFNegCombine()
4809 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res)); in performFNegCombine()
4815 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags()); in performFNegCombine()
4817 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags()); in performFNegCombine()
4822 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Res); in performFNegCombine()
4846 return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0)); in performFNegCombine()
4855 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags()); in performFNegCombine()
4862 return DAG.getNode(ISD::FP_ROUND, SL, VT, in performFNegCombine()
4871 return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1)); in performFNegCombine()
4920 SDValue Result = DAG.getNode(ISD::BITCAST, SL, VT, Build); in performFNegCombine()
4923 DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Result)); in performFNegCombine()
4927 if (BCSrc.getOpcode() == ISD::SELECT && VT == MVT::f32 && in performFNegCombine()
5203 EVT VT = N->getValueType(0); in PerformDAGCombine() local
5225 return DAG.getConstantFP(FTZ(V0), DL, VT); in PerformDAGCombine()
5239 Register Reg, EVT VT, in CreateLiveInRegister() argument
5254 return DAG.getRegister(VReg, VT); in CreateLiveInRegister()
5256 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, VReg, VT); in CreateLiveInRegister()
5274 EVT VT, in loadStackInputValue() argument
5279 int FI = getOrCreateFixedStackObject(MFI, VT.getStoreSize(), Offset); in loadStackInputValue()
5284 return DAG.getLoad(VT, SL, DAG.getEntryNode(), Ptr, SrcPtrInfo, Align(4), in loadStackInputValue()
5310 EVT VT, const SDLoc &SL, in loadInputValue() argument
5315 CreateLiveInRegister(DAG, RC, Arg.getRegister(), VT, SL) : in loadInputValue()
5316 loadStackInputValue(DAG, VT, SL, Arg.getStackOffset()); in loadInputValue()
5323 V = DAG.getNode(ISD::SRL, SL, VT, V, in loadInputValue()
5324 DAG.getShiftAmountConstant(Shift, VT, SL)); in loadInputValue()
5325 return DAG.getNode(ISD::AND, SL, VT, V, in loadInputValue()
5326 DAG.getConstant(Mask >> Shift, SL, VT)); in loadInputValue()
5525 EVT VT = Operand.getValueType(); in getSqrtEstimate() local
5527 if (VT == MVT::f32) { in getSqrtEstimate()
5529 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand); in getSqrtEstimate()
5541 EVT VT = Operand.getValueType(); in getRecipEstimate() local
5543 if (VT == MVT::f32) { in getRecipEstimate()
5550 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand); in getRecipEstimate()