Lines Matching refs:VT
228 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, in getFPLibCall() argument
235 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
236 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
237 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
238 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
239 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
569 MVT VT) { in getOUTLINE_ATOMIC() argument
570 if (!VT.isScalarInteger()) in getOUTLINE_ATOMIC()
572 uint64_t MemSize = VT.getScalarSizeInBits() / 8; in getOUTLINE_ATOMIC()
610 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC() argument
613 switch (VT.SimpleTy) { \ in getSYNC()
787 for (MVT VT : {MVT::i2, MVT::i4}) in initActions()
788 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; in initActions()
791 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) { in initActions()
792 setTruncStoreAction(AVT, VT, Expand); in initActions()
793 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); in initActions()
794 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); in initActions()
799 for (MVT VT : {MVT::i2, MVT::i4}) { in initActions()
800 setIndexedLoadAction(IM, VT, Expand); in initActions()
801 setIndexedStoreAction(IM, VT, Expand); in initActions()
802 setIndexedMaskedLoadAction(IM, VT, Expand); in initActions()
803 setIndexedMaskedStoreAction(IM, VT, Expand); in initActions()
807 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
808 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions()
810 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); in initActions()
811 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
816 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
820 setIndexedLoadAction(IM, VT, Expand); in initActions()
821 setIndexedStoreAction(IM, VT, Expand); in initActions()
822 setIndexedMaskedLoadAction(IM, VT, Expand); in initActions()
823 setIndexedMaskedStoreAction(IM, VT, Expand); in initActions()
827 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
847 VT, Expand); in initActions()
852 VT, Expand); in initActions()
857 VT, Expand); in initActions()
860 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
865 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, in initActions()
869 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); in initActions()
872 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, in initActions()
875 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
878 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, in initActions()
882 if (VT.isVector()) in initActions()
887 VT, Expand); in initActions()
891 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); in initActions()
895 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); in initActions()
905 VT, Expand); in initActions()
908 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
912 setOperationAction(ISD::SDOPC, VT, Expand); in initActions()
916 setOperationAction(ISD::GET_FPENV, VT, Expand); in initActions()
917 setOperationAction(ISD::SET_FPENV, VT, Expand); in initActions()
918 setOperationAction(ISD::RESET_FPENV, VT, Expand); in initActions()
953 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) { in initActions()
954 setOperationAction(ISD::GET_FPMODE, VT, Expand); in initActions()
955 setOperationAction(ISD::SET_FPMODE, VT, Expand); in initActions()
981 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { in canOpTrap()
982 assert(isTypeLegal(VT)); in canOpTrap()
1006 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { in getTypeConversion()
1008 if (VT.isSimple()) { in getTypeConversion()
1009 MVT SVT = VT.getSimpleVT(); in getTypeConversion()
1028 if (!VT.isVector()) { in getTypeConversion()
1029 assert(VT.isInteger() && "Float types must be simple"); in getTypeConversion()
1030 unsigned BitSize = VT.getSizeInBits(); in getTypeConversion()
1033 EVT NVT = VT.getRoundIntegerType(Context); in getTypeConversion()
1034 assert(NVT != VT && "Unable to round integer VT"); in getTypeConversion()
1044 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); in getTypeConversion()
1048 ElementCount NumElts = VT.getVectorElementCount(); in getTypeConversion()
1049 EVT EltVT = VT.getVectorElementType(); in getTypeConversion()
1061 if (!VT.isPow2VectorType()) { in getTypeConversion()
1073 if (VT.getVectorElementCount().isScalable()) in getTypeConversion()
1076 VT.getHalfNumVectorElementsVT(Context)); in getTypeConversion()
1131 if (!VT.isPow2VectorType()) { in getTypeConversion()
1132 EVT NVT = VT.getPow2VectorType(Context); in getTypeConversion()
1136 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) in getTypeConversion()
1141 VT.getVectorElementCount().divideCoefficientBy(2)); in getTypeConversion()
1145 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
1150 ElementCount EC = VT.getVectorElementCount(); in getVectorTypeBreakdownMVT()
1151 MVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdownMVT()
1157 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) in getVectorTypeBreakdownMVT()
1307 MVT VT) const { in findRepresentativeClass()
1308 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1459 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1460 if (isTypeLegal(VT)) in computeRegisterProperties()
1463 MVT EltVT = VT.getVectorElementType(); in computeRegisterProperties()
1464 ElementCount EC = VT.getVectorElementCount(); in computeRegisterProperties()
1466 bool IsScalable = VT.isScalableVector(); in computeRegisterProperties()
1467 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); in computeRegisterProperties()
1485 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); in computeRegisterProperties()
1508 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1517 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1520 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1533 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1540 MVT NVT = VT.getPow2VectorType(); in computeRegisterProperties()
1541 if (NVT == VT) { in computeRegisterProperties()
1545 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); in computeRegisterProperties()
1547 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1549 ValueTypeActions.setTypeAction(VT, TypeSplitVector); in computeRegisterProperties()
1551 ValueTypeActions.setTypeAction(VT, EC.isScalable() in computeRegisterProperties()
1556 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1580 EVT VT) const { in getSetCCResultType()
1581 assert(!VT.isVector() && "No default SetCC type for vectors!"); in getSetCCResultType()
1598 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1601 ElementCount EltCnt = VT.getVectorElementCount(); in getVectorTypeBreakdown()
1608 LegalizeTypeAction TA = getTypeAction(Context, VT); in getVectorTypeBreakdown()
1611 EVT RegisterEVT = getTypeToTransformTo(Context, VT); in getVectorTypeBreakdown()
1621 EVT EltTy = VT.getVectorElementType(); in getVectorTypeBreakdown()
1629 EVT PartVT = VT; in getVectorTypeBreakdown()
1642 divideCeil(VT.getVectorElementCount().getKnownMinValue(), in getVectorTypeBreakdown()
1728 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1740 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { in GetReturnInfo()
1742 if (VT.bitsLT(MinVT)) in GetReturnInfo()
1743 VT = MinVT; in GetReturnInfo()
1747 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1749 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); in GetReturnInfo()
1763 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
1776 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment() argument
1783 Type *Ty = VT.getTypeForEVT(Context); in allowsMemoryAccessForAlignment()
1784 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) { in allowsMemoryAccessForAlignment()
1792 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast); in allowsMemoryAccessForAlignment()
1796 LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccessForAlignment() argument
1798 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), in allowsMemoryAccessForAlignment()
1803 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1807 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, in allowsMemoryAccess()
1812 const DataLayout &DL, EVT VT, in allowsMemoryAccess() argument
1815 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), in allowsMemoryAccess()
1823 EVT VT = getApproximateEVTForLLT(Ty, DL, Context); in allowsMemoryAccess() local
1824 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), in allowsMemoryAccess()
2095 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { in getReciprocalOpName() argument
2096 std::string Name = VT.isVector() ? "vec-" : ""; in getReciprocalOpName()
2101 if (VT.getScalarType() == MVT::f64) { in getReciprocalOpName()
2103 } else if (VT.getScalarType() == MVT::f16) { in getReciprocalOpName()
2106 assert(VT.getScalarType() == MVT::f32 && in getReciprocalOpName()
2140 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { in getOpEnabled() argument
2173 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpEnabled()
2200 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { in getOpRefinementSteps() argument
2228 std::string VTName = getReciprocalOpName(IsSqrt, VT); in getOpRefinementSteps()
2246 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, in getRecipEstimateSqrtEnabled() argument
2248 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateSqrtEnabled()
2251 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, in getRecipEstimateDivEnabled() argument
2253 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); in getRecipEstimateDivEnabled()
2256 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, in getSqrtRefinementSteps() argument
2258 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); in getSqrtRefinementSteps()
2261 int TargetLoweringBase::getDivRefinementSteps(EVT VT, in getDivRefinementSteps() argument
2263 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); in getDivRefinementSteps()