Lines Matching refs:VT
184 bool isTypeLegal(Type *Ty, MVT &VT);
185 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
189 bool simplifyAddress(Address &Addr, MVT VT);
227 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
229 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
231 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
238 unsigned emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm);
267 unsigned materializeInt(const ConstantInt *CI, MVT VT);
268 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
319 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
320 switch (VT.SimpleTy) { in getImplicitScaleFactor()
373 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt() argument
374 if (VT > MVT::i64) in materializeInt()
378 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in materializeInt()
381 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
383 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
390 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP() argument
396 if (VT != MVT::f32 && VT != MVT::f64) in materializeFP()
400 bool Is64Bit = (VT == MVT::f64); in materializeFP()
407 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
420 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
438 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
543 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
547 assert(VT == MVT::i64 && "Expected 64-bit pointers"); in fastMaterializeConstant()
548 return materializeInt(ConstantInt::get(Type::getInt64Ty(*Context), 0), VT); in fastMaterializeConstant()
552 return materializeInt(CI, VT); in fastMaterializeConstant()
554 return materializeFP(CFP, VT); in fastMaterializeConstant()
564 MVT VT; in fastMaterializeFloatZero() local
565 if (!isTypeLegal(CFP->getType(), VT)) in fastMaterializeFloatZero()
568 if (VT != MVT::f32 && VT != MVT::f64) in fastMaterializeFloatZero()
571 bool Is64Bit = (VT == MVT::f64); in fastMaterializeFloatZero()
574 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg); in fastMaterializeFloatZero()
985 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() argument
994 VT = evt.getSimpleVT(); in isTypeLegal()
997 if (VT == MVT::f128) in isTypeLegal()
1002 return TLI.isTypeLegal(VT); in isTypeLegal()
1009 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported() argument
1013 if (isTypeLegal(Ty, VT)) in isTypeSupported()
1018 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) in isTypeSupported()
1032 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress() argument
1036 unsigned ScaleFactor = getImplicitScaleFactor(VT); in simplifyAddress()
1471 MVT VT = EVT.getSimpleVT(); in emitCmp() local
1473 switch (VT.SimpleTy) { in emitCmp()
1481 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1484 return emitFCmp(VT, LHS, RHS); in emitCmp()
1543 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) { in emitAdd_ri_() argument
1546 ResultReg = emitAddSub_ri(false, VT, Op0, -Imm); in emitAdd_ri_()
1548 ResultReg = emitAddSub_ri(true, VT, Op0, Imm); in emitAdd_ri_()
1553 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm); in emitAdd_ri_()
1557 ResultReg = emitAddSub_rr(true, VT, Op0, CReg); in emitAdd_ri_()
1650 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp() local
1651 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg); in emitLogicalOp()
1751 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1753 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitLoad()
1757 if (!simplifyAddress(Addr, VT)) in emitLoad()
1760 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitLoad()
1828 switch (VT.SimpleTy) { in emitLoad()
1868 if (VT == MVT::i1) { in emitLoad()
1876 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
1889 MVT VT; in selectAddSub() local
1890 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectAddSub()
1893 if (VT.isVector()) in selectAddSub()
1901 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1904 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1)); in selectAddSub()
1915 MVT VT; in selectLogicalOp() local
1916 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectLogicalOp()
1919 if (VT.isVector()) in selectLogicalOp()
1927 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1930 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1933 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1)); in selectLogicalOp()
1944 MVT VT; in selectLoad() local
1948 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) || in selectLoad()
1974 MVT RetVT = VT; in selectLoad()
1981 RetVT = VT; in selectLoad()
1986 RetVT = VT; in selectLoad()
1992 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
2015 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
2054 bool AArch64FastISel::emitStoreRelease(MVT VT, unsigned SrcReg, in emitStoreRelease() argument
2058 switch (VT.SimpleTy) { in emitStoreRelease()
2076 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, in emitStore() argument
2078 if (!TLI.allowsMisalignedMemoryAccesses(VT)) in emitStore()
2082 if (!simplifyAddress(Addr, VT)) in emitStore()
2085 unsigned ScaleFactor = getImplicitScaleFactor(VT); in emitStore()
2117 switch (VT.SimpleTy) { in emitStore()
2145 MVT VT; in selectStore() local
2150 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true)) in selectStore()
2173 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2176 VT = MVT::getIntegerVT(VT.getSizeInBits()); in selectStore()
2177 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2196 return emitStoreRelease(VT, SrcReg, AddrReg, in selectStore()
2206 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I))) in selectStore()
2273 MVT VT; in emitCompareAndBranch() local
2274 if (!isTypeSupported(LHS->getType(), VT)) in emitCompareAndBranch()
2277 unsigned BW = VT.getSizeInBits(); in emitCompareAndBranch()
2319 if (VT == MVT::i1) in emitCompareAndBranch()
2368 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*isZExt=*/true); in emitCompareAndBranch()
2670 MVT VT; in selectSelect() local
2671 if (!isTypeSupported(I->getType(), VT)) in selectSelect()
2676 switch (VT.SimpleTy) { in selectSelect()
2933 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments() local
2934 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8()) in fastLowerArguments()
2937 if (VT.isVector() && in fastLowerArguments()
2941 if (VT >= MVT::i1 && VT <= MVT::i64) in fastLowerArguments()
2943 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2944 VT.is128BitVector()) in fastLowerArguments()
2971 MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); in fastLowerArguments() local
2974 if (VT >= MVT::i1 && VT <= MVT::i32) { in fastLowerArguments()
2977 VT = MVT::i32; in fastLowerArguments()
2978 } else if (VT == MVT::i64) { in fastLowerArguments()
2981 } else if (VT == MVT::f16) { in fastLowerArguments()
2984 } else if (VT == MVT::f32) { in fastLowerArguments()
2987 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
2990 } else if (VT.is128BitVector()) { in fastLowerArguments()
3192 MVT VT; in fastLowerCall() local
3193 if (!isTypeLegal(Val->getType(), VT) && in fastLowerCall()
3194 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) in fastLowerCall()
3198 if (VT.isVector() || VT.getSizeInBits() > 64) in fastLowerCall()
3201 OutVTs.push_back(VT); in fastLowerCall()
3298 MVT VT; in tryEmitSmallMemCpy() local
3301 VT = MVT::i64; in tryEmitSmallMemCpy()
3303 VT = MVT::i32; in tryEmitSmallMemCpy()
3305 VT = MVT::i16; in tryEmitSmallMemCpy()
3307 VT = MVT::i8; in tryEmitSmallMemCpy()
3313 VT = MVT::i32; in tryEmitSmallMemCpy()
3315 VT = MVT::i16; in tryEmitSmallMemCpy()
3317 VT = MVT::i8; in tryEmitSmallMemCpy()
3321 unsigned ResultReg = emitLoad(VT, VT, Src); in tryEmitSmallMemCpy()
3325 if (!emitStore(VT, ResultReg, Dest)) in tryEmitSmallMemCpy()
3328 int64_t Size = VT.getSizeInBits() / 8; in tryEmitSmallMemCpy()
3582 MVT VT; in fastLowerIntrinsicCall() local
3583 if (!isTypeLegal(II->getType(), VT)) in fastLowerIntrinsicCall()
3587 switch (VT.SimpleTy) { in fastLowerIntrinsicCall()
3600 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3618 MVT VT; in fastLowerIntrinsicCall() local
3619 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3626 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg); in fastLowerIntrinsicCall()
3644 MVT VT; in fastLowerIntrinsicCall() local
3645 if (!isTypeLegal(RetTy, VT)) in fastLowerIntrinsicCall()
3648 if (VT != MVT::i32 && VT != MVT::i64) in fastLowerIntrinsicCall()
3683 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3687 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3691 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3695 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3708 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3711 fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3718 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3721 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3722 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3723 emitSubs_rs(VT, SMULHReg, MulReg, AArch64_AM::ASR, 63, in fastLowerIntrinsicCall()
3738 if (VT == MVT::i32) { in fastLowerIntrinsicCall()
3745 MulReg = fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3747 assert(VT == MVT::i64 && "Unexpected value type."); in fastLowerIntrinsicCall()
3750 MulReg = emitMul_rr(VT, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3751 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3752 emitSubs_rr(VT, AArch64::XZR, UMULHReg, /*WantResult=*/false); in fastLowerIntrinsicCall()
3759 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
4641 MVT VT; in selectMul() local
4642 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true)) in selectMul()
4645 if (VT.isVector()) in selectMul()
4658 MVT SrcVT = VT; in selectMul()
4662 MVT VT; in selectMul() local
4663 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) { in selectMul()
4664 SrcVT = VT; in selectMul()
4671 MVT VT; in selectMul() local
4672 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) { in selectMul()
4673 SrcVT = VT; in selectMul()
4685 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt); in selectMul()
4701 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); in selectMul()
4875 MVT VT; in selectSDiv() local
4876 if (!isTypeLegal(I->getType(), VT)) in selectSDiv()
4883 if ((VT != MVT::i32 && VT != MVT::i64) || !C || in selectSDiv()
4893 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2); in selectSDiv()
4901 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
4906 if (!emitICmp_ri(VT, Src0Reg, 0)) in selectSDiv()
4911 if (VT == MVT::i64) { in selectSDiv()
4925 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4928 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
4931 ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2); in selectSDiv()
4974 MVT VT = TLI.getPointerTy(DL); in selectGetElementPtr() local
4994 N = emitAdd_ri_(VT, N, TotalOffs); in selectGetElementPtr()
5007 unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize); in selectGetElementPtr()
5010 IdxN = emitMul_rr(VT, IdxN, C); in selectGetElementPtr()
5014 N = fastEmit_rr(VT, VT, ISD::ADD, N, IdxN); in selectGetElementPtr()
5020 N = emitAdd_ri_(VT, N, TotalOffs); in selectGetElementPtr()
5037 MVT VT; in selectAtomicCmpXchg() local
5038 if (!isTypeLegal(RetTy, VT)) in selectAtomicCmpXchg()
5045 if (VT == MVT::i32) { in selectAtomicCmpXchg()
5049 } else if (VT == MVT::i64) { in selectAtomicCmpXchg()
5079 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()