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Searched refs:getOperand (Results 1 – 25 of 810) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/X86/InstPrinter/
H A DX86InstComments.cpp524 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
540 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
556 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
570 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
588 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
682 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
700 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
1124 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1125 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1134 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
64 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
65 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
66 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
88 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorLoad()
89 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
98 .addReg(MI->getOperand(1).getReg()) in lowerSubvectorStore()
99 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp190 unsigned Reg2 = MI.getOperand(2).getReg(); in processBlock()
246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
252 MI.getOperand(3).setSubReg(AddSubReg); in processBlock()
255 MI.getOperand(3).setIsKill(AddRegKill); in processBlock()
258 MI.getOperand(3).setIsUndef(AddRegUndef); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
266 MI.getOperand(2).setSubReg(AddSubReg); in processBlock()
267 MI.getOperand(2).setIsKill(AddRegKill); in processBlock()
[all …]
H A DPPCMIPeephole.cpp149 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
155 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
365 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); in simplifyCode()
366 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); in simplifyCode()
387 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
559 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
603 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
645 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg())) in simplifyCode()
1105 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) { in eliminateRedundantCompare()
1131 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { in eliminateRedundantCompare()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp86 HiLUI.getOperand(1).getOffset() != 0 || in detectLuiAddiGlobal()
94 LoADDI->getOperand(2).getOffset() != 0 || in detectLuiAddiGlobal()
107 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
108 LoADDI.getOperand(2).setOffset(Offset); in foldOffset()
111 MRI->replaceRegWith(Tail.getOperand(0).getReg(), in foldOffset()
139 unsigned Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset()
140 unsigned Rt = TailAdd.getOperand(2).getReg(); in matchLargeOffset()
193 int64_t Offset = Tail.getOperand(2).getImm(); in detectAndFoldOffset()
232 if (Tail.getOperand(1).isFI()) in detectAndFoldOffset()
242 HiLUI.getOperand(1).setOffset(Offset); in detectAndFoldOffset()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp137 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
154 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
162 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) { in mergeIfPossible()
163 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
165 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
167 RootCFAlu.getOperand(KBank0LineIdx) in mergeIfPossible()
171 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
173 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
[all …]
H A DAMDGPURegisterBankInfo.cpp68 return isConstant(Def->getOperand(1), C); in isConstant()
260 if (!MI.getOperand(i).isReg()) in isSALUMapping()
262 unsigned Reg = MI.getOperand(i).getReg(); in isSALUMapping()
299 if (MI.getOperand(OpdIdx).isIntrinsicID()) in getDefaultMappingVOP()
302 unsigned Reg1 = MI.getOperand(OpdIdx).getReg(); in getDefaultMappingVOP()
505 unsigned Dst = MI.getOperand(0).getReg(); in getInstrMapping()
506 unsigned Src = MI.getOperand(1).getReg(); in getInstrMapping()
517 unsigned Dst = MI.getOperand(0).getReg(); in getInstrMapping()
518 unsigned Src = MI.getOperand(1).getReg(); in getInstrMapping()
547 if (!MI.getOperand(i).isReg()) in getInstrMapping()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp88 const MCOperand &Dst = MI->getOperand(0); in printInst()
89 const MCOperand &MO1 = MI->getOperand(1); in printInst()
90 const MCOperand &MO2 = MI->getOperand(2); in printInst()
91 const MCOperand &MO3 = MI->getOperand(3); in printInst()
111 const MCOperand &Dst = MI->getOperand(0); in printInst()
153 MI->getOperand(3).getImm() == -4) { in printInst()
182 MI->getOperand(4).getImm() == 4) { in printInst()
277 switch (MI->getOperand(0).getImm()) { in printInst()
933 if (MI->getOperand(OpNum).getReg()) { in printSBitModifierOperand()
943 O << MI->getOperand(OpNum).getImm(); in printNoHashImmediate()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp167 MIBHI->getOperand(4).setIsKill(); in expandArith()
192 MIBLO->getOperand(3).setIsDead(); in expandLogic()
313 MIBHI->getOperand(4).setIsKill(); in expand()
345 MIBLO->getOperand(4).setIsKill(); in expand()
356 MIBHI->getOperand(4).setIsKill(); in expand()
404 MIBLO->getOperand(2).setIsDead(); in expand()
827 auto Op1 = MI.getOperand(0); in expandAtomicBinaryOp()
828 auto Op2 = MI.getOperand(1); in expandAtomicBinaryOp()
847 auto Op1 = MI.getOperand(0); in expandAtomicArithmeticOp()
848 auto Op2 = MI.getOperand(1); in expandAtomicArithmeticOp()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2), N->getOperand(3) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
185 N->getOperand(2), N->getOperand(3) }; in Select()
191 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
192 N->getOperand(2), N->getOperand(3) }; in Select()
198 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in Select()
241 SDValue Chain = N->getOperand(0); in tryBRIND()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp212 Rt = L.getOperand(0); in getCompoundInsn()
223 Rt = L.getOperand(0); in getCompoundInsn()
224 Rs = L.getOperand(1); in getCompoundInsn()
237 Rs = L.getOperand(1); in getCompoundInsn()
238 Rt = L.getOperand(2); in getCompoundInsn()
250 Rs = L.getOperand(1); in getCompoundInsn()
251 Rt = L.getOperand(2); in getCompoundInsn()
263 Rs = L.getOperand(1); in getCompoundInsn()
264 Rt = L.getOperand(2); in getCompoundInsn()
284 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
H A DHexagonMCDuplexInfo.cpp203 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
204 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
221 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
222 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
242 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
243 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
252 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
253 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
262 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
263 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp63 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
71 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
117 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
118 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
769 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
784 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
798 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
812 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
856 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
869 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm11()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp969 N->getOperand(1), N->getOperand(2)); in performSETCCCombine()
983 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); in performVSELECTCombine()
1581 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1596 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1600 Op->getOperand(2), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1641 Op->getOperand(1), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1864 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1874 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); in lowerINTRINSIC_WO_CHAIN()
1924 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); in lowerINTRINSIC_WO_CHAIN()
1942 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
[all …]
H A DMicroMipsSizeReduction.cpp311 if (!MI->getOperand(Op).isImm()) in GetImm()
372 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in CheckXWPInstr()
449 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()
518 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUR1SP()
536 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUSP()
665 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) && in ReduceXORtoXOR16()
666 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in ReduceXORtoXOR16()
715 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
718 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
719 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/InstPrinter/
H A DLanaiInstPrinter.cpp47 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
54 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
59 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
64 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
149 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
162 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
176 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
188 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
200 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
237 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2121 N0 == N1.getOperand(1).getOperand(0)) in visitADD()
2127 N0 == N1.getOperand(1).getOperand(1)) in visitADD()
2134 N0 == N1.getOperand(0).getOperand(1)) in visitADD()
2679 N0.getOperand(1).getOperand(0) == N1) in visitSUB()
2685 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
2691 N0.getOperand(1).getOperand(1) == N1) in visitSUB()
3892 N0.getOperand(1) == N1.getOperand(1)) { in hoistLogicOpWithSameOpcodeHands()
11953 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), in visitSINT_TO_FP()
11955 N0.getOperand(0).getOperand(2) }; in visitSINT_TO_FP()
16499 Op0.getOperand(0).getOperand(0) == Op.getOperand(0).getOperand(0)) in convertBuildVecZextToZext()
[all …]
H A DLegalizeFloatTypes.cpp835 if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2)) in SoftenFloatOp_COPY_TO_REG()
879 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); in SoftenFloatOp_BR_CC()
914 if (Op0 == N->getOperand(0) && Op1 == N->getOperand(1)) in SoftenFloatOp_FCOPYSIGN()
962 if (Op1 == N->getOperand(1) && Op2 == N->getOperand(2)) in SoftenFloatOp_SELECT()
970 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); in SoftenFloatOp_SELECT_CC()
993 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); in SoftenFloatOp_SETCC()
1201 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; in ExpandFloatRes_FDIV()
1275 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; in ExpandFloatRes_FMA()
1289 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; in ExpandFloatRes_FMUL()
1404 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; in ExpandFloatRes_FSUB()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1026 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3)); in expandPostRAPseudo()
2582 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() && in isToBeScheduledASAP()
2583 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg()) in isToBeScheduledASAP()
3716 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3829 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
3865 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3873 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3968 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) in getDuplexCandidateGroup()
3977 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) in getDuplexCandidateGroup()
3998 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) || in getDuplexCandidateGroup()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp347 MachineOperand &RegOp = I.getOperand(1); in selectFP16CopyFromGPR32()
681 MovZ->addOperand(MF, I.getOperand(1)); in materializeLargeCMVal()
776 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{}; in select()
911 } else if (I.getOperand(1).isImm()) { in select()
942 .addDef(I.getOperand(0).getReg()) in select()
946 I.getOperand(0).setReg(DstReg); in select()
977 .addUse(I.getOperand(2).getReg()) in select()
981 I.getOperand(2).setReg(SrcReg); in select()
1087 I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex()); in select()
1275 I.getOperand(1).setReg(ExtSrc); in select()
[all …]
H A DAArch64AsmPrinter.cpp457 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); in PrintDebugValueComment()
544 int JTIdx = MI.getOperand(4).getIndex(); in LowerJumpTableDestSmall()
738 MI->getOperand(1).getImm() == 0) { in EmitInstruction()
905 assert(MI->getOperand(0).getImm() < 0 && in EmitInstruction()
916 assert(MI->getOperand(1).getImm() < 0 && in EmitInstruction()
923 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in EmitInstruction()
930 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in EmitInstruction()
932 assert(MI->getOperand(2).getImm() < 0 && in EmitInstruction()
944 assert(MI->getOperand(1).getImm() < 0 && in EmitInstruction()
951 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) && in EmitInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/InstPrinter/
H A DPPCInstPrinter.cpp72 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
95 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
180 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
313 int Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
364 if (MI->getOperand(OpNo).isImm()) in printS16ImmOperand()
365 O << (short)MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
372 if (MI->getOperand(OpNo).isImm()) in printU16ImmOperand()
380 if (!MI->getOperand(OpNo).isImm()) in printBranchOperand()
394 if (!MI->getOperand(OpNo).isImm()) in printAbsBranchOperand()
447 const MCOperand &Op = MI->getOperand(OpNo); in printTLSCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
72 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo()
89 if (MI.getOperand(OI).getReg() == ARM::SP || in getARMStoreDeprecationInfo()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5002 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
6773 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in validateInstruction()
7211 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm())) in processInstruction()
7216 if (Inst.getOperand(2).isImm()) { in processInstruction()
8457 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
8719 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || in processInstruction()
8768 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { in processInstruction()
9013 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && in processInstruction()
9048 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || in processInstruction()
9049 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && in processInstruction()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp641 MachineOperand &MO = MI.getOperand(OpIdx); in widenScalarSrc()
643 MO.setReg(ExtB->getOperand(0).getReg()); in widenScalarSrc()
648 MachineOperand &MO = MI.getOperand(OpIdx); in widenScalarDst()
721 MI.getOperand(1).setReg(MIBNewOp->getOperand(0).getReg()); in widenScalar()
857 MachineOperand &SrcMO = MI.getOperand(1); in widenScalar()
982 .addUse(MI.getOperand(1).getReg()) in lower()
983 .addUse(MI.getOperand(2).getReg()); in lower()
987 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), in lower()
1063 .addUse(MI.getOperand(1).getReg()); in lower()
1325 Op = MIBOp->getOperand(0).getReg(); in lowerBitCount()
[all …]

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